Inventor

DELAYE ELLIOTT

US36 patents

⚠️ This page may combine multiple inventors who share the name “DELAYE ELLIOTT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DELAYE ELLIOTT

XILINX INC

Data format suitable for fast massively parallel general matrix multiplication in a programmable IC

Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit

Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC

Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructions

Circuit arrangements and methods for performing multiply-and-accumulate operations

Neural network processing system having multiple processors and a neural network accelerator

Software-driven design optimization for fixed-point multiply-accumulate circuitry

Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators

Circuit arrangements and methods for traversing input feature maps

Software-defined buffer/transposer for general matrix multiplication in a programmable IC

Circuit arrangements and methods for dividing a three-dimensional input feature map

Object identification in an electronic circuit design

Software defined neural network layer pipelining

Neural network processing system having host controlled kernel acclerators

Host-directed multi-layer neural network processing via per-layer work requests

Image preprocessing for generalized image processing

Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit

Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions

Selecting predefined circuit implementations in a circuit design system

Compact and efficient circuit implementation of dynamic ranges in hardware description languages

Parallelizing timing-based operations for circuit designs

Circuits for and methods of enabling the modification of an input data stream

Hardware acceleration of machine learning designs

Scalable acceleration of reentrant compute operations

Reconfigurable neural engine with extensible instruction set architecture

Static block scheduling in massively parallel software defined hardware systems

Machine learning runtime library for neural network acceleration

Data-driven pattern matching in synthesis of circuit designs

Instruction set architecture for data processing array control

CSWITCH CORP

Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes

Dedicated logic cells employing configurable logic and dedicated logic functions

Dedicated logic cells employing configurable logic and dedicated logic functions

Dedicated logic cells employing configurable logic and dedicated logic functions

VELOGIX INC

Programmable logic and routing blocks with dedicated lines

CSITCH CORP

Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes

AGATE LOGIC INC

Dedicated logic cells employing configurable logic and dedicated logic functions