Inventor · disambiguated record
Robert J. Divivier
Also filed as: DIVIVIER ROBERT · DIVIVIER ROBERT J · DIVIVIER ROBERT JAMES
21 granted patents·807 citations·filing 1995–2008
97Inventor score
Files withINTEGRATED DEVICE TECH8NAT SEMICONDUCTOR CORP7CISCO TECH IND2ZETTACOM INC2DIVIVIER ROBERT1
Top patents by PatentIndex Score
21 records- 0193US6959002B2Traffic manager for network switch portINTEGRATED DEVICE TECH·Filed 2001·Granted Oct 25, 2005·125 cites·20 claims
- 0290US6687781B2Fair weighted queuing bandwidth allocation system for network switch portZETTACOM INC·Filed 2001·Granted Feb 3, 2004·75 cites·18 claims
- 0388US7454554B1Binary base address search device and methodINTEGRATED DEVICE TECH·Filed 2006·Granted Nov 18, 2008·20 cites·22 claims
- 0488US7079485B1Multiservice switching system with distributed switch fabricINTEGRATED DEVICE TECH·Filed 2001·Granted Jul 18, 2006·69 cites·18 claims
- 0587US7058070B2Back pressure control system for network switch portINTEGRATED DEVICE TECH·Filed 2001·Granted Jun 6, 2006·56 cites·13 claims
- 0686US7181485B1Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuitsINTEGRATED DEVICE TECH·Filed 2001·Granted Feb 20, 2007·46 cites·29 claims
- 0784US7647438B1Binary base address sorting method and device with shift vectorINTEGRATED DEVICE TECH·Filed 2006·Granted Jan 12, 2010·16 cites·22 claims
- 0881US7058057B2Network switch port traffic manager having configurable packet and cell servicingINTEGRATED DEVICE TECH·Filed 2001·Granted Jun 6, 2006·38 cites·12 claims
- 0978US7356722B2Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuitsINTERGRATED DEVICE TECHNOLOGY·Filed 2007·Granted Apr 8, 2008·9 cites·19 claims
- 1075US6598132B2Buffer manager for network switch portZETTACOM INC·Filed 2001·Granted Jul 22, 2003·24 cites·19 claims
- 1174US6237074B1Tagged prefetch and instruction decoder for variable length instruction set and method of operationNAT SEMICONDUCTOR CORP·Filed 1995·Granted May 22, 2001·72 cites·13 claims
- 1274US5680564APipelined processor with two tier prefetch buffer structure and method with bypassNAT SEMICONDUCTOR CORP·Filed 1995·Granted Oct 21, 1997·69 cites·31 claims
- 1372US7110405B2Multicast cell buffer for network switchINTEGRATED DEVICE TECH·Filed 2001·Granted Sep 19, 2006·16 cites·23 claims
- 1468US5774684AIntegrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access and control arbitrationNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jun 30, 1998·53 cites·19 claims
- 1562US5752269APipelined microprocessor that pipelines memory requests to an external memoryNAT SEMICONDUCTOR CORP·Filed 1995·Granted May 12, 1998·45 cites·18 claims
- 1659US9467307B2Method of tracking arrival order of packets into plural queuesDIVIVIER ROBERT·Filed 2008·Granted Oct 11, 2016·2 cites·21 claims
- 1752US5752273AApparatus and method for efficiently determining addresses for misaligned data stored in memoryNAT SEMICONDUCTOR CORP·Filed 1997·Granted May 12, 1998·27 cites·10 claims
- 1843US6618382B1Auto early packet discard (EPD) mechanism for automatically enabling EPD on an asynchronous transfer mode (ATM) networkCISCO TECH IND·Filed 1999·Granted Sep 9, 2003·16 cites·54 claims
- 1942US5717909ACode breakpoint decoderNAT SEMICONDUCTOR CORP·Filed 1995·Granted Feb 10, 1998·17 cites·14 claims
- 2034US6212181B1Method for using the departure queue memory bandwidth to support additional cell arrivals in an ATM switchCISCO TECH IND·Filed 1999·Granted Apr 3, 2001·7 cites·8 claims
- 2130US5659712APipelined microprocessor that prevents the cache from being read when the contents of the cache are invalidNAT SEMICONDUCTOR CORP·Filed 1995·Granted Aug 19, 1997·5 cites·19 claims
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