Inventor · disambiguated record
Sudhakar Surendran
Also filed as: SURENDRAN SUDHAKAR
15 granted patents·4 pending applications·22 citations·filing 2009–2025
88Inventor score
Top patents by PatentIndex Score
19 records- 0189US11334701B2Method for comprehensive integration verification of mixed-signal circuitsTEXAS INSTRUMENTS INC·Filed 2021·Granted May 17, 2022·2 cites·11 claims
- 0286US10949594B2Method for comprehensive integration verification of mixed-signal circuitsTEXAS INSTRUMENTS INC·Filed 2019·Granted Mar 16, 2021·3 cites·11 claims
- 0386US8112652B2Multiprocessor system power management of shared memories powering down memory bank only when all processors indicate not powering that memory bankSAJAYAN SAJISH·Filed 2009·Granted Feb 7, 2012·12 cites·3 claims
- 0483US2025350269A1Dynamic control of a multi-trim oscillatorTEXAS INSTRUMENTS INC·Filed 2025·Application pending·0 cites
- 0581US11531798B2Methods and apparatus to simulate metastability for circuit design verificationTEXAS INSTRUMENTS INC·Filed 2021·Granted Dec 20, 2022·1 cites·20 claims
- 0679US10489538B2Method for comprehensive integration verification of mixed-signal circuitsTEXAS INSTRUMENTS INC·Filed 2016·Granted Nov 26, 2019·2 cites·18 claims
- 0776US12375070B2Dynamic control of a multi-trim oscillatorTEXAS INSTRUMENTS INC·Filed 2023·Granted Jul 29, 2025·0 cites·20 claims
- 0874US2025103789A1Techniques for modeling and verification of convergence for hierarchical domain crossingsTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 0973US11669668B2Method for comprehensive integration verification of mixed-signal circuitsTEXAS INSTRUMENTS INC·Filed 2022·Granted Jun 6, 2023·0 cites·11 claims
- 1072US11775718B2Methods and apparatus to simulate metastability for circuit design verificationTEXAS INSTRUMENTS INC·Filed 2022·Granted Oct 3, 2023·0 cites·20 claims
- 1167US12197840B2Techniques for modeling and verification of convergence for hierarchical domain crossingsTEXAS INSTRUMENTS INC·Filed 2021·Granted Jan 14, 2025·0 cites·20 claims
- 1266US12510920B2Managing clock trigger signals for asynchronous clock domainsTEXAS INSTRUMENTS INC·Filed 2023·Granted Dec 30, 2025·0 cites·20 claims
- 1365US8078897B2Power management in federated/distributed shared memory architectureSAJAYAN SAJISH·Filed 2009·Granted Dec 13, 2011·2 cites·4 claims
- 1459US12321674B2Hierarchical CDC and RDC verificationTEXAS INSTRUMENTS INC·Filed 2022·Granted Jun 3, 2025·0 cites·20 claims
- 1558US12181974B2Techniques for peripheral utilization metrics collection and reportingTEXAS INSTRUMENTS INC·Filed 2021·Granted Dec 31, 2024·0 cites·19 claims
- 1656US12326466B2Identifying glitches and levels in mixed-signal waveformsINDIAN INSTITUTE OF TECH KHARAGPUR·Filed 2022·Granted Jun 10, 2025·0 cites·22 claims
- 1752US8117398B2Prefetch termination at powered down memory bank boundary in shared memory controllerSAJAYAN SAJISH·Filed 2009·Granted Feb 14, 2012·0 cites·4 claims
- 1846US2023110701A1Techniques for design verification of domain crossingsTEXAS INSTRUMENTS INC·Filed 2021·Application pending·0 cites
- 1942US2024193337A1Tracking coverage artifacts for periodic signals using sequence-based abstractionsINDIAN INSTITUTE OF TECH KHARAGPUR·Filed 2022·Application pending·0 cites
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