Inventor · disambiguated record
Brian D. Philofsky
Also filed as: PHILOFSKY BRIAN · PHILOFSKY BRIAN D
13 granted patents·154 citations·filing 2005–2021
92Inventor score
Top patents by PatentIndex Score
13 records- 0197US11373929B1Thermal heat spreader plate for electronic deviceXILINX INC·Filed 2020·Granted Jun 28, 2022·13 cites·20 claims
- 0296US10262920B1Stacked silicon package having a thermal capacitance elementXILINX INC·Filed 2016·Granted Apr 16, 2019·24 cites·21 claims
- 0396US9812374B1Thermal management device with textured surface for extended cooling limitXILINX INC·Filed 2017·Granted Nov 7, 2017·18 cites·20 claims
- 0495US11950358B1Integrated circuit package with voltage droop mitigationXILINX INC·Filed 2021·Granted Apr 2, 2024·3 cites·20 claims
- 0593US7274211B1Structures and methods for implementing ternary adders/subtractors in programmable logic devicesXILINX INC·Filed 2006·Granted Sep 25, 2007·38 cites·20 claims
- 0692US10147664B2Dynamic mounting thermal management for devices on boardXILINX INC·Filed 2017·Granted Dec 4, 2018·10 cites·24 claims
- 0791US11328976B1Three-dimensional thermal management apparatuses for electronic devicesXILINX INC·Filed 2020·Granted May 10, 2022·3 cites·10 claims
- 0888US8104012B1System and methods for reducing clock power in integrated circuitsKLEIN MATTHEW H·Filed 2009·Granted Jan 24, 2012·21 cites·20 claims
- 0978US8010923B1Latch based optimization during implementation of circuit designs for programmable logic devicesXILINX INC·Filed 2008·Granted Aug 30, 2011·7 cites·16 claims
- 1078US7451417B1Timing annotation accuracy through the use of static timing analysis toolsXILINX INC·Filed 2006·Granted Nov 11, 2008·10 cites·13 claims
- 1168US7421675B1Annotating timing information for a circuit design for increased timing accuracyXILINX INC·Filed 2006·Granted Sep 2, 2008·5 cites·13 claims
- 1254US7653677B1Digital logic circuit for adding three binary words and method of implementing sameXILINX INC·Filed 2005·Granted Jan 26, 2010·2 cites·18 claims
- 1348US8146041B1Latch based optimization during implementation of circuit designs for programmable logic devicesSRINIVASAN SANKARANARAYANAN·Filed 2011·Granted Mar 27, 2012·0 cites·10 claims
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