Inventor · disambiguated record
Toru Osajima
Also filed as: OSAJIMA TORU
12 granted patents·57 citations·filing 1997–2010
89Inventor score
Top patents by PatentIndex Score
12 records- 0167US6622293B1Method and system for designing wire layout without causing antenna errorFUJITSU LTD·Filed 2000·Granted Sep 16, 2003·13 cites·18 claims
- 0259US8519551B2Semiconductor device with I/O cell and external connection terminal and method of manufacturing the sameOSAJIMA TORU·Filed 2010·Granted Aug 27, 2013·2 cites·20 claims
- 0358US6467070B2Design support apparatus for semiconductor devicesFUJITSU LTD·Filed 2001·Granted Oct 15, 2002·9 cites·13 claims
- 0457US6603158B1Semiconductor integrated circuit having high-density base cell arrayFUJITSU LTD·Filed 2000·Granted Aug 5, 2003·8 cites·7 claims
- 0553US6881989B2Semiconductor integrated circuit having high-density base cell arrayFUJITSU LTD·Filed 2003·Granted Apr 19, 2005·6 cites·5 claims
- 0648US6885046B2Semiconductor integrated circuit configured to supply sufficient internal currentFUJITSU LTD·Filed 2002·Granted Apr 26, 2005·3 cites·1 claims
- 0742US7146592B2Integrated logic circuit and hierarchical design method thereofFUJITSU LTD·Filed 2005·Granted Dec 5, 2006·0 cites·3 claims
- 0839US6501106B1Semiconductor integrated circuit device and method of producing the sameFUJITSU LTD·Filed 1999·Granted Dec 31, 2002·6 cites·6 claims
- 0938US6604229B2Method of designing wiring for power sources in a semiconductor chip, and a computer productFUJITSU LTD·Filed 2001·Granted Aug 5, 2003·0 cites·36 claims
- 1037US6013924ASemiconductor integrated circuit and method for making wiring layout of semiconductor integrated circuitFUJITSU LTD·Filed 1997·Granted Jan 11, 2000·8 cites·13 claims
- 1135US6924666B2Integrated logic circuit and hierarchical design method thereofFUJITSU LTD·Filed 2002·Granted Aug 2, 2005·0 cites·6 claims
- 1228US6207980B1Layout method of a semiconductor deviceFUJITSU LTD·Filed 1999·Granted Mar 27, 2001·2 cites·18 claims
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