Inventor · disambiguated record
Pranav Ashar
Also filed as: ASHAR PRANAV · ASHAR PRANAV N
33 granted patents·5 pending applications·1,641 citations·filing 1992–2019
98Inventor score
Top patents by PatentIndex Score
38 records- 0198US7346486B2System and method for modeling, abstraction, and analysis of softwareNEC LAB AMERICA INC·Filed 2005·Granted Mar 18, 2008·283 cites·2 claims
- 0295US6975976B1Property specific testbench generation framework for circuit design validation by guided simulationNEC CORP·Filed 2000·Granted Dec 13, 2005·98 cites·43 claims
- 0394US7383166B2Verification of scheduling in the presence of loops using uninterpreted symbolic simulationNEC CORP·Filed 2004·Granted Jun 3, 2008·86 cites·10 claims
- 0492US7019674B2Content-based information retrieval architectureNEC LAB AMERICA INC·Filed 2004·Granted Mar 28, 2006·91 cites·42 claims
- 0592US6816825B1Simulation vector generation from HDL descriptions for observability-enhanced statement coverageNEC CORP·Filed 1999·Granted Nov 9, 2004·98 cites·45 claims
- 0689US6496961B2Dynamic detection and removal of inactive clauses in SAT with application in image computationNEC USA INC·Filed 2001·Granted Dec 17, 2002·40 cites·13 claims
- 0787US6745160B1Verification of scheduling in the presence of loops using uninterpreted symbolic simulationNEC CORP·Filed 1999·Granted Jun 1, 2004·115 cites·33 claims
- 0885US6651234B2Partition-based decision heuristics for SAT and image computation using SAT and BDDsNEC CORP·Filed 2001·Granted Nov 18, 2003·42 cites·27 claims
- 0983US6728665B1SAT-based image computation with application in reachability analysisNEC CORP·Filed 2000·Granted Apr 27, 2004·34 cites·28 claims
- 1081US6163876AMethod for verification of RTL generated from scheduled behavior in a high-level synthesis flowNEC USA INC·Filed 1998·Granted Dec 19, 2000·103 cites·8 claims
- 1178US8131532B2Software verification using range analysisCADAMBI SRIHARI·Filed 2006·Granted Mar 6, 2012·12 cites·8 claims
- 1277US6038392AImplementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardwareNEC USA INC·Filed 1998·Granted Mar 14, 2000·79 cites·12 claims
- 1377US6026222ASystem for combinational equivalence checkingNEC USA INC·Filed 1997·Granted Feb 15, 2000·82 cites·9 claims
- 1476US7742907B2Iterative abstraction using SAT-based BMC with proof analysisNEC LAB AMERICA INC·Filed 2004·Granted Jun 22, 2010·22 cites·7 claims
- 1576US7386818B2Efficient modeling of embedded memories in bounded memory checkingNEC LAB AMERICA INC·Filed 2005·Granted Jun 10, 2008·10 cites·22 claims
- 1675US6324673B1Method and apparatus for edge-endpoint-based VLSI design rule checkingUNIV PRINCETON·Filed 1999·Granted Nov 27, 2001·76 cites·51 claims
- 1772US7711525B2Efficient approaches for bounded model checkingNEC CORP·Filed 2002·Granted May 4, 2010·18 cites·21 claims
- 1870US10690722B1Methods and systems for efficient identification of glitch failures in integrated circuitsASHAR PRANAV·Filed 2019·Granted Jun 23, 2020·3 cites·16 claims
- 1969US7305637B2Efficient SAT-based unbounded symbolic model checkingNEC LAB AMERICA INC·Filed 2005·Granted Dec 4, 2007·4 cites·28 claims
- 2068US5522063AMethod of finding minimum-cost feedback-vertex sets for a graph for partial scan testing without exhaustive cycle enumerationNEC USA INC·Filed 1993·Granted May 28, 1996·27 cites·26 claims
- 2163US5448497AExploiting multi-cycle false paths in the performance optimization of sequential circuitsNEC RESEARCH INST INC·Filed 1992·Granted Sep 5, 1995·39 cites·6 claims
- 2262US6415430B1Method and apparatus for SAT solver architecture with very low synthesis and layout overheadNEC USA INC·Filed 1999·Granted Jul 2, 2002·42 cites·24 claims
- 2361US9965575B2Methods and systems for correcting X-pessimism in gate-level simulation or emulationASHAR PRANAV·Filed 2016·Granted May 8, 2018·1 cites·19 claims
- 2461US7203917B2Efficient distributed SAT and SAT-based distributed bounded model checkingNEC LAB AMERICA INC·Filed 2004·Granted Apr 10, 2007·7 cites·27 claims
- 2561US6874135B2Method for design validation using retimingNEC CORP·Filed 1999·Granted Mar 29, 2005·36 cites·12 claims
- 2661US6035109AMethod for using complete-1-distinguishability for FSM equivalence checkingNEC USA INC·Filed 1997·Granted Mar 7, 2000·39 cites·10 claims
- 2760US6247164B1Configurable hardware system implementing Boolean Satisfiability and method thereofNEC USA INC·Filed 1997·Granted Jun 12, 2001·39 cites·15 claims
- 2858US5937183AEnhanced binary decision diagram-based functional simulationNEC USA INC·Filed 1996·Granted Aug 10, 1999·33 cites·21 claims
- 2957US6662323B1Fast error diagnosis for combinational verificationNEC CORP·Filed 1999·Granted Dec 9, 2003·16 cites·7 claims
- 3048US6816827B1Verification method for combinational loop systemsNIPPON ELECTRIC CO·Filed 1999·Granted Nov 9, 2004·20 cites·8 claims
- 3143US2005149301A1Method for design validation using retimingNEC CORP·Filed 2005·Application pending·0 cites
- 3242US6223141B1Speeding up levelized compiled code simulation using netlist transformationsNEC USA INC·Filed 1998·Granted Apr 24, 2001·14 cites·36 claims
- 3342US2003105617A1Hardware acceleration system for logic simulationNEC USA INC·Filed 2002·Application pending·0 cites
- 3442US2006206744A1Low-power high-throughput streaming computationsNEC LAB AMERICA INC·Filed 2005·Application pending·0 cites
- 3541US5457638ATiming analysis of VLSI circuitsNEC RESEARCH INSTITUE INC·Filed 1993·Granted Oct 10, 1995·16 cites·1 claims
- 3639US5748486ABreadth-first manipulation of binary decision diagramsNEC USA INC·Filed 1994·Granted May 5, 1998·16 cites·15 claims
- 3739US2008065639A1String matching engineNETFORTIS INC·Filed 2006·Application pending·0 cites
- 3839US2008052644A1String matching engine for arbitrary length stringsNETFORTIS INC·Filed 2006·Application pending·0 cites
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