Inventor · disambiguated record
Yeong-Jyh T. Lii
Also filed as: LII YEONG JYH · LII YEONG-JYH T · LII YEONG-JYH TOM
16 granted patents·1 pending application·831 citations·filing 1993–2004
95Inventor score
Top patents by PatentIndex Score
17 records- 0196US6362071B1Method for forming a semiconductor device with an opening in a dielectric layerMOTOROLA INC·Filed 2000·Granted Mar 26, 2002·149 cites·20 claims
- 0295US6369430B1Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the sameMOTOROLA INC·Filed 2001·Granted Apr 9, 2002·121 cites·14 claims
- 0390US6287951B1Process for forming a combination hardmask and antireflective layerMOTOROLA INC·Filed 1998·Granted Sep 11, 2001·164 cites·20 claims
- 0486US6004850ATantalum oxide anti-reflective coating (ARC) integrated with a metallic transistor gate electrode and method of formationMOTOROLA INC·Filed 1998·Granted Dec 21, 1999·58 cites·23 claims
- 0586US5378312AProcess for fabricating a semiconductor structure having sidewallsIBM·Filed 1993·Granted Jan 3, 1995·103 cites·17 claims
- 0684US5888588AProcess for forming a semiconductor deviceMOTOROLA INC·Filed 1997·Granted Mar 30, 1999·62 cites·27 claims
- 0780US6838354B2Method for forming a passivation layer for air gap formationFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Jan 4, 2005·24 cites·17 claims
- 0877US6146948AMethod for manufacturing a thin oxide for use in semiconductor integrated circuitsMOTOROLA INC·Filed 1997·Granted Nov 14, 2000·42 cites·30 claims
- 0976US6294820B1Metallic oxide gate electrode stack having a metallic gate dielectric metallic gate electrode and a metallic arc layerMOTOROLA INC·Filed 1999·Granted Sep 25, 2001·33 cites·8 claims
- 1070US6686633B1Semiconductor device, memory cell, and processes for forming themMOTOROLA INC·Filed 2000·Granted Feb 3, 2004·16 cites·20 claims
- 1169US6815820B2Method for forming a semiconductor interconnect with multiple thicknessFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Nov 9, 2004·14 cites·16 claims
- 1264US6184073B1Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or regionMOTOROLA INC·Filed 1997·Granted Feb 6, 2001·27 cites·14 claims
- 1352US6891229B2Inverted isolation formed with spacersFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted May 10, 2005·6 cites·20 claims
- 1452US6774053B1Method and structure for low-k dielectric constant applicationsFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Aug 10, 2004·5 cites·11 claims
- 1549US7176574B2Semiconductor device having a multiple thickness interconnectFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Feb 13, 2007·3 cites·7 claims
- 1648US6689676B1Method for forming a semiconductor device structure in a semiconductor layerMOTOROLA INC·Filed 2002·Granted Feb 10, 2004·4 cites·15 claims
- 1729US2002171107A1Method for forming a semiconductor device having elevated source and drain regionsFiled 2001·Application pending·0 cites
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