Inventor · disambiguated record
Martin S. Schmookler
Also filed as: SCHMOOKLER MARTIN S · SCHMOOKLER MARTIN STANLEY
30 granted patents·5 pending applications·681 citations·filing 1986–2023
97Inventor score
Top patents by PatentIndex Score
35 records- 0187US4903228ASingle cycle merge/logic unitIBM·Filed 1988·Granted Feb 20, 1990·99 cites·8 claims
- 0285US7451172B2Handling denormal floating point operands when result must be normalizedIBM·Filed 2005·Granted Nov 11, 2008·16 cites·1 claims
- 0383US12223290B2Decimal floating-point instruction in a round-for-reround modeIBM·Filed 2023·Granted Feb 11, 2025·0 cites·25 claims
- 0482US7730117B2System and method for a floating point unit with feedback prior to normalization and roundingIBM·Filed 2005·Granted Jun 1, 2010·13 cites·20 claims
- 0582US6240433B1High accuracy estimates of elementary functionsIBM·Filed 2000·Granted May 29, 2001·40 cites·2 claims
- 0679US8429217B2Executing fixed point divide operations using a floating point multiply-add pipelineSCHMOOKLER MARTIN STANLEY·Filed 2008·Granted Apr 23, 2013·11 cites·13 claims
- 0775US8402078B2Method, system and computer program product for determining required precision in fixed-point divide operationsWEINBERG JOSHUA M·Filed 2008·Granted Mar 19, 2013·8 cites·18 claims
- 0875US8260837B2Handling denormal floating point operands when result must be normalizedPOWELL JR LAWRENCE JOSEPH·Filed 2008·Granted Sep 4, 2012·9 cites·3 claims
- 0975US5826070AApparatus and method for maintaining status flags and condition codes using a renaming technique in an out of order floating point execution unitIBM·Filed 1996·Granted Oct 20, 1998·75 cites·10 claims
- 1074US5930148AMethod and system for verifying a digital circuit design including dynamic circuit cells that utilize diverse circuit techniquesIBM·Filed 1996·Granted Jul 27, 1999·78 cites·23 claims
- 1173US11698772B2Prepare for shorter precision (round for reround) mode in a decimal floating-point instructionIBM·Filed 2020·Granted Jul 11, 2023·0 cites·25 claims
- 1271US8024647B2Method and system for checking rotate, shift and sign extension functions using a modulo functionIBM·Filed 2008·Granted Sep 20, 2011·4 cites·22 claims
- 1370US6684232B1Method and predictor for streamlining execution of convert-to-integer operationsIBM·Filed 2000·Granted Jan 27, 2004·15 cites·20 claims
- 1467US8713084B2Method, system and computer program product for verifying floating point divide operation resultsWEINBERG JOSHUA M·Filed 2008·Granted Apr 29, 2014·4 cites·15 claims
- 1565US5493520ATwo state leading zero/one anticipator (LZA)IBM·Filed 1994·Granted Feb 20, 1996·42 cites·16 claims
- 1664US8626816B2Method, system and computer program product for detecting errors in fixed point division operation resultsWEINBERG JOSHUA M·Filed 2008·Granted Jan 7, 2014·3 cites·11 claims
- 1764US6178435B1Method and system for performing a power of two estimation within a data processing systemIBM·Filed 1998·Granted Jan 23, 2001·44 cites·6 claims
- 1863US5957997AEfficient floating point normalization mechanismIBM·Filed 1997·Granted Sep 28, 1999·43 cites·20 claims
- 1960US7376890B2Method and system for checking rotate, shift and sign extension functions using a modulo functionIBM·Filed 2004·Granted May 20, 2008·6 cites·10 claims
- 2059US6163791AHigh accuracy estimates of elementary functionsIBM·Filed 1998·Granted Dec 19, 2000·35 cites·31 claims
- 2158US5129066ABit mask generator circuit using multiple logic units for generating a bit mask sequenceIBM·Filed 1989·Granted Jul 7, 1992·23 cites·15 claims
- 2249US6182100B1Method and system for performing a logarithmic estimation within a data processing systemIBM·Filed 1998·Granted Jan 30, 2001·21 cites·8 claims
- 2349US5790444AFast alignment unit for multiply-add floating point unitIBM·Filed 1996·Granted Aug 4, 1998·23 cites·10 claims
- 2448US8745118B2Verifying floating point square root operation resultsWEINBERG JOSHUA M·Filed 2008·Granted Jun 3, 2014·0 cites·15 claims
- 2547US2006179092A1System and method for executing fixed point divide operations using a floating point multiply-add pipelineSCHMOOKLER MARTIN S·Filed 2005·Application pending·0 cites
- 2646US2006047738A1Decimal rounding mode which preserves data information for further rounding to less precisionIBM·Filed 2004·Application pending·0 cites
- 2745US5764549AFast floating point result alignment apparatusIBM·Filed 1996·Granted Jun 9, 1998·18 cites·6 claims
- 2844US4771284ALogic array with programmable element output generationIBM·Filed 1986·Granted Sep 13, 1988·6 cites·4 claims
- 2943US5539332AAdder circuits and magnitude comparatorIBM·Filed 1994·Granted Jul 23, 1996·14 cites·12 claims
- 3042US5528601AScannable latch for multiplexor controlIBM·Filed 1994·Granted Jun 18, 1996·9 cites·8 claims
- 3142US4766565AArithmetic logic circuit having a carry generatorIBM·Filed 1986·Granted Aug 23, 1988·11 cites·15 claims
- 3242US2006179096A1System and method for a fused multiply-add dataflow with early feedback prior to roundingIBM·Filed 2005·Application pending·0 cites
- 3341US2006184603A1Zero detect in partial sums while addingTRONG SON D·Filed 2005·Application pending·0 cites
- 3439US5636156AAdder with improved carry lookahead structureIBM·Filed 1996·Granted Jun 3, 1997·11 cites·7 claims
- 3533US2012173923A1Accelerating the performance of mathematical functions in high performance computer systemsENENKEL ROBERT F·Filed 2010·Application pending·0 cites
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