Inventor · disambiguated record
Tsair-Chin Lin
Also filed as: LIN TSAIR-CHIN
11 granted patents·2 pending applications·106 citations·filing 2003–2022
89Inventor score
Files withCADENCE DESIGN SYSTEMS INC7XEPIC CORPORATION LTD2QUICKTURN DESIGN SYSTEMS INC1SARKISIAN ARTHUR PERRY1TUNG TUNG-SUN1
Top patents by PatentIndex Score
13 records- 0195US10909283B1Hardware assisted weighted toggle countCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Feb 2, 2021·29 cites·21 claims
- 0290US8352235B1Emulation of power shutoff behavior for integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jan 8, 2013·29 cites·27 claims
- 0381US8812286B1Emulation of power shutoff behavior for integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Aug 19, 2014·6 cites·22 claims
- 0481US8108194B2Peak power detection in digital designs using emulation systemsZHU BING·Filed 2008·Granted Jan 31, 2012·14 cites·27 claims
- 0580US10198539B1Systems and methods for dynamic RTL monitors in emulation systemsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Feb 5, 2019·3 cites·20 claims
- 0676US8453086B2System and method for analyzing power consumption of electronic design undergoing emulation or hardware based simulation accelerationTUNG TUNG-SUN·Filed 2006·Granted May 28, 2013·13 cites·35 claims
- 0770US9400858B1Virtual verification machine for a hardware based verification platformCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jul 26, 2016·3 cites·21 claims
- 0870US8739090B1Probe signal compression method and apparatus for hardware based verification platformsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted May 27, 2014·3 cites·28 claims
- 0962US8898051B2System and method for implementing a trace interfaceSARKISIAN ARTHUR PERRY·Filed 2010·Granted Nov 25, 2014·2 cites·16 claims
- 1052US11537504B2Realization of functional verification debug station via cross-platform record-mapping-replay technologyXEPIC CORPORATION LTD·Filed 2020·Granted Dec 27, 2022·0 cites·25 claims
- 1151US7440884B2Memory rewind and reconstruction for hardware emulatorQUICKTURN DESIGN SYSTEMS INC·Filed 2003·Granted Oct 21, 2008·4 cites·10 claims
- 1250US2022413042A1Debug system and debug methodXEPIC CORPORATION LTD·Filed 2022·Application pending·0 cites
- 1343US2014173539A1Method and Apparatus for Isolating and/or Debugging Defects in Integrated Circuit DesignsCADENCE DESIGN SYSTEMS INC·Filed 2012·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →