Inventor · disambiguated record
Ryan Keech
Also filed as: KEECH RYAN
18 granted patents·8 pending applications·16 citations·filing 2018–2025
90Inventor score
Top patents by PatentIndex Score
26 records- 0184US11804523B2High aspect ratio source or drain structures with abrupt dopant profileINTEL CORP·Filed 2019·Granted Oct 31, 2023·3 cites·18 claims
- 0284US11610889B2Arsenic-doped epitaxial, source/drain regions for NMOSINTEL CORP·Filed 2018·Granted Mar 21, 2023·3 cites·15 claims
- 0382US12388011B2Top gate recessed channel CMOS thin film transistor and methods of fabricationINTEL CORP·Filed 2023·Granted Aug 12, 2025·0 cites·18 claims
- 0482US11328988B2Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabricationINTEL CORP·Filed 2019·Granted May 10, 2022·2 cites·17 claims
- 0581US11244943B2Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel materialINTEL CORP·Filed 2019·Granted Feb 8, 2022·2 cites·21 claims
- 0680US12119387B2Low resistance approaches for fabricating contacts and the resulting structuresINTEL CORP·Filed 2020·Granted Oct 15, 2024·1 cites·10 claims
- 0780US11552169B2Source or drain structures with phosphorous and arsenic co-dopantsINTEL CORP·Filed 2019·Granted Jan 10, 2023·2 cites·25 claims
- 0878US11164785B2Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain materialINTEL CORP·Filed 2019·Granted Nov 2, 2021·2 cites·15 claims
- 0977US2025227956A1Contact resistance reduction in transistor devices with metallization on both sidesINTEL CORP·Filed 2025·Application pending·0 cites
- 1077US2024347610A1Contact resistance reduction in transistor devices with metallization on both sidesINTEL CORP·Filed 2024·Application pending·0 cites
- 1176US12342611B2Source or drain structures with vertical trenchesINTEL CORP·Filed 2024·Granted Jun 24, 2025·0 cites·20 claims
- 1275US12288808B2High aspect ratio source or drain structures with abrupt dopant profileINTEL CORP·Filed 2023·Granted Apr 29, 2025·0 cites·20 claims
- 1374US11929320B2Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabricationINTEL CORP·Filed 2022·Granted Mar 12, 2024·0 cites·19 claims
- 1473US12094881B2Arsenic-doped epitaxial source/drain regions for NMOSINTEL CORP·Filed 2023·Granted Sep 17, 2024·0 cites·17 claims
- 1572US2024258427A1Source or drain structures for germanium n-channel devicesINTEL CORP·Filed 2024·Application pending·0 cites
- 1671US11935887B2Source or drain structures with vertical trenchesINTEL CORP·Filed 2019·Granted Mar 19, 2024·1 cites·16 claims
- 1769US11996404B2Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel materialINTEL CORP·Filed 2021·Granted May 28, 2024·0 cites·18 claims
- 1868US12342574B2Contact resistance reduction in transistor devices with metallization on both sidesINTEL CORP·Filed 2020·Granted Jun 24, 2025·0 cites·16 claims
- 1955US11973143B2Source or drain structures for germanium N-channel devicesINTEL CORP·Filed 2019·Granted Apr 30, 2024·0 cites·15 claims
- 2053US12266570B2Self-aligned interconnect structures and methods of fabricationINTEL CORP·Filed 2020·Granted Apr 1, 2025·0 cites·20 claims
- 2148US11482621B2Vertically stacked CMOS with upfront M0 interconnectINTEL CORP·Filed 2018·Granted Oct 25, 2022·0 cites·16 claims
- 2248US2023095191A1Transistors with reduced epitaxial source/drain span via etch-back for improved cell scalingINTEL CORP·Filed 2021·Application pending·0 cites
- 2347US2022199402A1Source & drain dopant diffusion barriers for n-type germanium transistorsINTEL CORP·Filed 2020·Application pending·0 cites
- 2444US2021408283A1Gate-all-around integrated circuit structures having strained source or drain structures on insulatorINTEL CORP·Filed 2020·Application pending·0 cites
- 2544US2021408284A1Gate-all-around integrated circuit structures having strained source or drain structures on gate dielectric layerINTEL CORP·Filed 2020·Application pending·0 cites
- 2643US2021407996A1Gate-all-around integrated circuit structures having strained dual nanoribbon channel structuresAGRAWAL ASHISH·Filed 2020·Application pending·0 cites
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