Inventor · disambiguated record
Shreekanth Sampigethaya
Also filed as: SAMPIGETHAYA SHREEKANTH · SAMPIGETHAYA SHREEKANTH K · SAMPIGETHAYA SHREEKANTH KARANDOOR
9 granted patents·69 citations·filing 2001–2016
86Inventor score
Files withADVANCED MICRO DEVICES INC2SAMPIGETHAYA SHREEKANTH2TAIWAN SEMICONDUCTOR MFG2VIRAGE LOGIC CORP2TAIWAN SEMICONDUCTOR MFG CO LTD1
Top patents by PatentIndex Score
9 records- 0184US8362807B2Offset compensation for sense amplifiersTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Jan 29, 2013·8 cites·15 claims
- 0284US6396760B1Memory having a redundancy scheme to allow one fuse to blow per faulty memory columnVIRAGE LOGIC CORP·Filed 2001·Granted May 28, 2002·39 cites·30 claims
- 0381US7251186B1Multi-port memory utilizing an array of single-port memory cellsVIRAGE LOGIC CORP·Filed 2005·Granted Jul 31, 2007·15 cites·18 claims
- 0469US9509255B2Offset compensation for sense amplifiersTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Nov 29, 2016·2 cites·20 claims
- 0568US9710589B2Using a cut mask to form spaces representing spacing violations in a semiconductor structureADVANCED MICRO DEVICES INC·Filed 2015·Granted Jul 18, 2017·2 cites·17 claims
- 0661US9898568B2Reducing the load on the bitlines of a ROM bitcell arrayADVANCED MICRO DEVICES INC·Filed 2015·Granted Feb 20, 2018·1 cites·15 claims
- 0755US9322859B2Offset compensation for sense amplifiersTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted Apr 26, 2016·1 cites·20 claims
- 0849US8213242B2Memory cells having a row-based read and/or write support circuitrySAMPIGETHAYA SHREEKANTH·Filed 2010·Granted Jul 3, 2012·1 cites·19 claims
- 0938US8630134B2Memory cells having a row-based read and/or write support circuitrySAMPIGETHAYA SHREEKANTH·Filed 2012·Granted Jan 14, 2014·0 cites·19 claims
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