Inventor · disambiguated record
John Caywood
Also filed as: CAYWOOD JOHN · CAYWOOD JOHN M · CAYWOOD JOHN MILLARD
28 granted patents·1 pending application·1,579 citations·filing 1974–2002
98Inventor score
Files withCAYWOOD JOHN M4TEXAS INSTRUMENTS INC4JOHN MILLARD AND PAMELA ANN CA3CAYWOOD JOHN2CREDENCE SYSTEMS CORP2
Top patents by PatentIndex Score
29 records- 0194US5986931ALow voltage single CMOS electrically erasable read-only memoryFiled 1997·Granted Nov 16, 1999·105 cites·14 claims
- 0294US5153880AField-programmable redundancy apparatus for memory arraysXICOR INC·Filed 1990·Granted Oct 6, 1992·152 cites·27 claims
- 0394US3934161AElectronic shutter for a charge-coupled imagerTEXAS INSTRUMENTS INC·Filed 1974·Granted Jan 20, 1976·61 cites·19 claims
- 0493US5790455ALow voltage single supply CMOS electrically erasable read-only memoryCAYWOOD JOHN M·Filed 1997·Granted Aug 4, 1998·116 cites·35 claims
- 0591US6534816B1Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cellCAYWOOD JOHN M·Filed 2000·Granted Mar 18, 2003·68 cites·65 claims
- 0691US6479863B2Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cellCAYWOOD JOHN M·Filed 2000·Granted Nov 12, 2002·54 cites·43 claims
- 0791US5764096AGeneral purpose, non-volatile reprogrammable switchGATEFIELD CORP·Filed 1996·Granted Jun 9, 1998·98 cites·15 claims
- 0891US5235544AFlash EPROM cell and method for operating sameCAYWOOD JOHN·Filed 1990·Granted Aug 10, 1993·93 cites·2 claims
- 0990US6384451B1Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cellCAYWOOD JOHN·Filed 2000·Granted May 7, 2002·57 cites·59 claims
- 1089US6411545B1Non-volatile latchJOHN MILLARD AND PAMELA ANN CA·Filed 2000·Granted Jun 25, 2002·59 cites·5 claims
- 1189US6201732B1Low voltage single CMOS electrically erasable read-only memoryFiled 2000·Granted Mar 13, 2001·55 cites·22 claims
- 1289US3943543AThree level electrode configuration for three phase charge coupled deviceTEXAS INSTRUMENTS INC·Filed 1974·Granted Mar 9, 1976·39 cites·12 claims
- 1387US5974579AEfficient built-in self test for embedded memories with differing address spacesCREDENCE SYSTEMS CORP·Filed 1996·Granted Oct 26, 1999·74 cites·22 claims
- 1486US6574140B2Low voltage single supply CMOS electrically erasable read-only memoryJOHN MILLARD AND PAMELA ANN CA·Filed 2000·Granted Jun 3, 2003·39 cites·14 claims
- 1586US5270980ASector erasable flash EEPROMEASTMAN KODAK CO·Filed 1991·Granted Dec 14, 1993·60 cites·3 claims
- 1683US3944849ACharge transfer device signal processingTEXAS INSTRUMENTS INC·Filed 1974·Granted Mar 16, 1976·28 cites·20 claims
- 1782US6451652B1Method for forming an EEPROM cell together with transistor for peripheral circuitsJOHN MILLARD AND PAMELA ANN CA·Filed 2000·Granted Sep 17, 2002·34 cites·11 claims
- 1882US4072977ARead only memory utilizing charge coupled device structuresTEXAS INSTRUMENTS INC·Filed 1976·Granted Feb 7, 1978·27 cites·7 claims
- 1980US6745370B1Method for selecting an optimal level of redundancy in the design of memoriesHEURISTICS PHYSICS LAB INC·Filed 2000·Granted Jun 1, 2004·29 cites·8 claims
- 2078US5621738AMethod for programming flash EEPROM devicesEASTMAN KODAK CO·Filed 1991·Granted Apr 15, 1997·42 cites·2 claims
- 2178US5475695AAutomatic failure analysis systemSEMICONDUCTOR DIAGNOSIS & TEST·Filed 1993·Granted Dec 12, 1995·108 cites·9 claims
- 2278US5161157AField-programmable redundancy apparatus for memory arraysXICOR INC·Filed 1991·Granted Nov 3, 1992·84 cites·37 claims
- 2369US6920596B2Method and apparatus for determining fault sources for device failuresHEURISTICS PHYSICS LAB INC·Filed 2002·Granted Jul 19, 2005·16 cites·11 claims
- 2469US6092030ATiming delay generator and method including compensation for environmental variationCREDENCE SYSTEMS CORP·Filed 1997·Granted Jul 18, 2000·31 cites·15 claims
- 2561US5070480ANonvolatile associative memory systemCAYWOOD JOHN M·Filed 1990·Granted Dec 3, 1991·20 cites·23 claims
- 2657US6096093AMethod for using inspection data for improving throughput of stepper operations in manufacturing of integrated circuitsHEURISTIC PHYSICS LAB·Filed 1997·Granted Aug 1, 2000·24 cites·13 claims
- 2746US6780656B2Correction of overlay offset between inspection layersHPL TECHNOLOGIES INC·Filed 2001·Granted Aug 24, 2004·2 cites·18 claims
- 2846US4122550ALow power random access memory with self-refreshing cellsINTEL CORP·Filed 1978·Granted Oct 24, 1978·4 cites·16 claims
- 2934US2004021170A1Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cellFiled 2001·Application pending·0 cites
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