Inventor · disambiguated record
Julie Segal
Also filed as: SEGAL JULIE · SEGAL JULIE D · SEGAL JULIE DIANE
8 granted patents·1 pending application·313 citations·filing 1997–2019
88Inventor score
Files withHEURISTICS PHYSICS LAB INC3HPL TECHNOLOGIES INC2CREDENCE SYSTEMS CORP1HUERISTICS PHYSICS LAB1SPANSION LLC1
Top patents by PatentIndex Score
9 records- 0193US6795953B2Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit designHPL TECHNOLOGIES INC·Filed 2002·Granted Sep 21, 2004·195 cites·7 claims
- 0280US6745370B1Method for selecting an optimal level of redundancy in the design of memoriesHEURISTICS PHYSICS LAB INC·Filed 2000·Granted Jun 1, 2004·29 cites·8 claims
- 0380US6701477B1Method for identifying the cause of yield loss in integrated circuit manufactureHUERISTICS PHYSICS LAB·Filed 2000·Granted Mar 2, 2004·28 cites·2 claims
- 0469US6920596B2Method and apparatus for determining fault sources for device failuresHEURISTICS PHYSICS LAB INC·Filed 2002·Granted Jul 19, 2005·16 cites·11 claims
- 0569US6092030ATiming delay generator and method including compensation for environmental variationCREDENCE SYSTEMS CORP·Filed 1997·Granted Jul 18, 2000·31 cites·15 claims
- 0663US6810510B2Method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layoutHEURISTICS PHYSICS LAB INC·Filed 2002·Granted Oct 26, 2004·12 cites·20 claims
- 0746US11295962B2Low temperature process for diode termination of fully depleted high resistivity silicon radiation detectors that can be used for shallow entrance windows and thinned sensorsUNIV LELAND STANFORD JUNIOR·Filed 2019·Granted Apr 5, 2022·0 cites·11 claims
- 0846US6780656B2Correction of overlay offset between inspection layersHPL TECHNOLOGIES INC·Filed 2001·Granted Aug 24, 2004·2 cites·18 claims
- 0945US2010055809A1Process of fabricating a workpiece using a test maskSPANSION LLC·Filed 2008·Application pending·0 cites
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