Inventor · disambiguated record
Hwong-Kwo Lin
Also filed as: LIN HWONG-KWO · LIN HWONG-KWO HANK
29 granted patents·1 pending application·224 citations·filing 2006–2015
96Inventor score
Top patents by PatentIndex Score
30 records- 0193US7643330B1Sequentially-accessed 1R/1W double-pumped single port SRAM with shared decoder architectureNVIDIA CORP·Filed 2007·Granted Jan 5, 2010·40 cites·20 claims
- 0291US7839170B1Low power single rail input voltage level shifterNVIDIA CORP·Filed 2009·Granted Nov 23, 2010·20 cites·14 claims
- 0390US7626878B1Active bit line charge keeperNVIDIA CORP·Filed 2007·Granted Dec 1, 2009·27 cites·20 claims
- 0487US9355710B2Hybrid approach to write assist for memory arrayNVIDIA CORP·Filed 2014·Granted May 31, 2016·15 cites·18 claims
- 0587US9183922B2Eight transistor (8T) write assist static random access memory (SRAM) cellNVIDIA CORP·Filed 2013·Granted Nov 10, 2015·11 cites·11 claims
- 0687US7626854B12-write 3-read SRAM design using a 12-T storage cellNVIDIA CORP·Filed 2007·Granted Dec 1, 2009·18 cites·21 claims
- 0783US9542992B2SRAM core cell design with write assistNVIDIA CORP·Filed 2013·Granted Jan 10, 2017·9 cites·18 claims
- 0883US8866528B2Dual flip-flop circuitNVIDIA CORP·Filed 2012·Granted Oct 21, 2014·7 cites·19 claims
- 0982US7463065B1Low power single-rail-input voltage level shifterNVIDIA CORP·Filed 2006·Granted Dec 9, 2008·10 cites·8 claims
- 1081US7626871B1High-speed single-ended memory read circuitNVIDIA CORP·Filed 2007·Granted Dec 1, 2009·12 cites·24 claims
- 1178US9110141B2Flip-flop circuit having a reduced hold time requirement for a scan inputNVIDIA CORP·Filed 2012·Granted Aug 18, 2015·4 cites·17 claims
- 1275US7768320B1Process variation tolerant sense amplifier flop designNVIDIA CORP·Filed 2007·Granted Aug 3, 2010·9 cites·20 claims
- 1374US7772891B1Self-timed dynamic sense amplifier flop circuit apparatus and methodNVIDIA CORP·Filed 2007·Granted Aug 10, 2010·10 cites·19 claims
- 1471US7649762B1Area efficient high performance memory cellNVIDIA CORP·Filed 2006·Granted Jan 19, 2010·4 cites·19 claims
- 1571US7583126B2Apparatus and method for preventing current leakage when a low voltage domain is powered downNVIDIA CORP·Filed 2007·Granted Sep 1, 2009·6 cites·18 claims
- 1668US9496047B2Memory cell and memoryYANG JUN·Filed 2013·Granted Nov 15, 2016·3 cites·20 claims
- 1768US7492204B1Generic flexible timer designNVIDIA CORP·Filed 2007·Granted Feb 17, 2009·6 cites·22 claims
- 1866US7830175B1Low power single-rail-input voltage level shifterNVIDIA CORP·Filed 2008·Granted Nov 9, 2010·4 cites·6 claims
- 1964US9484115B1Power savings via selection of SRAM power sourceNVIDIA CORP·Filed 2015·Granted Nov 1, 2016·2 cites·20 claims
- 2063US10672461B2Write assist negative bit line voltage generator for SRAM arrayNVIDIA CORP·Filed 2014·Granted Jun 2, 2020·3 cites·16 claims
- 2158US9525401B2Low clocking power flip-flopNVIDIA CORP·Filed 2015·Granted Dec 20, 2016·1 cites·20 claims
- 2256US8988123B2Small area low power data retention flopNVIDIA CORP·Filed 2012·Granted Mar 24, 2015·1 cites·8 claims
- 2354US7772885B1Level shifter circuit to shift signals from a logic voltage to an input/output voltageNVIDIA CORP·Filed 2009·Granted Aug 10, 2010·2 cites·20 claims
- 2448US9219480B2Low tau synchronizer flip-flop with dual loop feedback approach to improve mean time between failureNVIDIA CORP·Filed 2014·Granted Dec 22, 2015·0 cites·20 claims
- 2547US7504872B2Generic flexible timer designNVIDIA CORP·Filed 2007·Granted Mar 17, 2009·0 cites·20 claims
- 2644US9123438B2Configurable delay circuit and method of clock bufferingNVIDIA CORP·Filed 2013·Granted Sep 1, 2015·0 cites·14 claims
- 2742US9390788B2Configurable delay circuit and method of clock bufferingNVIDIA CORP·Filed 2015·Granted Jul 12, 2016·0 cites·14 claims
- 2838US9842631B2Mitigating external influences on long signal linesNVIDIA CORP·Filed 2012·Granted Dec 12, 2017·0 cites·17 claims
- 2937US2015235681A1Pseudo-differential read scheme for dual port ramNVIDIA CORP·Filed 2014·Application pending·0 cites
- 3034US10181842B2Mixed threshold flip-flop element to mitigate hold time penalty due to clock distortionNVIDIA CORP·Filed 2015·Granted Jan 15, 2019·0 cites·25 claims
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