Inventor · disambiguated record
Dean G. Bair
Also filed as: BAIR DEAN G · BAIR DEAN GILBERT
22 granted patents·307 citations·filing 1995–2021
95Inventor score
Top patents by PatentIndex Score
22 records- 0187US10061679B2Evaluating fairness in devices under testIBM·Filed 2015·Granted Aug 28, 2018·4 cites·12 claims
- 0284US7089518B2Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocksIBM·Filed 2004·Granted Aug 8, 2006·41 cites·16 claims
- 0381US10055327B2Evaluating fairness in devices under testIBM·Filed 2014·Granted Aug 21, 2018·4 cites·19 claims
- 0481US6119219ASystem serialization with early release of individual processorIBM·Filed 1998·Granted Sep 12, 2000·98 cites·13 claims
- 0580US8271932B2Hierarchical error injection for complex RAIM/ECC designBAIR DEAN G·Filed 2010·Granted Sep 18, 2012·10 cites·21 claims
- 0679US9892010B2Persistent command parameter table for pre-silicon device testingIBM·Filed 2016·Granted Feb 13, 2018·2 cites·1 claims
- 0779US9524801B2Persistent command parameter table for pre-silicon device testingIBM·Filed 2016·Granted Dec 20, 2016·2 cites·1 claims
- 0878US9619312B2Persistent command parameter table for pre-silicon device testingIBM·Filed 2015·Granted Apr 11, 2017·2 cites·19 claims
- 0978US6865645B1Program store compare handling between instruction and operand cachesIBM·Filed 2000·Granted Mar 8, 2005·27 cites·25 claims
- 1076US6079013AMultiprocessor serialization with early release of processorsIBM·Filed 1998·Granted Jun 20, 2000·76 cites·11 claims
- 1173US10289512B2Persistent command parameter table for pre-silicon device testingIBM·Filed 2017·Granted May 14, 2019·1 cites·1 claims
- 1269US5745386ATiming diagram method for inputting logic design parameters to build a testcase for the logic diagramIBM·Filed 1995·Granted Apr 28, 1998·32 cites·13 claims
- 1362US10678670B2Evaluating fairness in devices under testIBM·Filed 2018·Granted Jun 9, 2020·0 cites·20 claims
- 1462US10671506B2Evaluating fairness in devices under testIBM·Filed 2018·Granted Jun 2, 2020·0 cites·20 claims
- 1561US7996203B2Method, system, and computer program product for out of order instruction address stride prefetch performance verificationIBM·Filed 2008·Granted Aug 9, 2011·2 cites·20 claims
- 1655US11748238B2Model-based biased random system test through rest APIIBM·Filed 2021·Granted Sep 5, 2023·0 cites·20 claims
- 1755US6560687B1Method of implementing a translation lookaside buffer with support for a real space controlIBM·Filed 2000·Granted May 6, 2003·4 cites·16 claims
- 1853US9990290B2Cache coherency verification using ordered listsIBM·Filed 2017·Granted Jun 5, 2018·0 cites·20 claims
- 1953US9665280B2Cache coherency verification using ordered listsIBM·Filed 2014·Granted May 30, 2017·0 cites·14 claims
- 2049US9665281B2Cache coherency verification using ordered listsIBM·Filed 2015·Granted May 30, 2017·0 cites·8 claims
- 2147US7559002B2Multi-thread parallel segment scan simulation of chip element performanceIBM·Filed 2007·Granted Jul 7, 2009·0 cites·1 claims
- 2239US7213122B2Controlling the generation and selection of addresses to be used in a verification environmentIBM·Filed 2004·Granted May 1, 2007·2 cites·31 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →