Inventor · disambiguated record
Minh Van Ngo
Also filed as: VAN NGO MINH
13 granted patents·313 citations·filing 1997–2010
93Inventor score
Top patents by PatentIndex Score
13 records- 0192US6764951B1Method for forming nitride capped Cu lines with reduced hillock formationADVANCED MICRO DEVICES INC·Filed 2002·Granted Jul 20, 2004·67 cites·15 claims
- 0288US6153523AMethod of forming high density capping layers for copper interconnects with improved adhesionADVANCED MICRO DEVICES INC·Filed 1998·Granted Nov 28, 2000·90 cites·20 claims
- 0384US8415256B1Gap-filling with uniform propertiesNICKEL ALEXANDER·Filed 2010·Granted Apr 9, 2013·9 cites·14 claims
- 0484US7071086B2Method of forming a metal gate structure with tuning of work function by silicon incorporationADVANCED MICRO DEVICES INC·Filed 2003·Granted Jul 4, 2006·32 cites·14 claims
- 0574US5963841AGate pattern formation using a bottom anti-reflective coatingADVANCED MICRO DEVICES INC·Filed 1997·Granted Oct 5, 1999·45 cites·18 claims
- 0672US6297148B1Method of forming a silicon bottom anti-reflective coating with reduced junction leakage during salicidationADVANCED MICRO DEVICES INC·Filed 2000·Granted Oct 2, 2001·18 cites·12 claims
- 0771US6406996B1Sub-cap and method of manufacture therefor in integrated circuit capping layersADVANCED MICRO DEVICES INC·Filed 2000·Granted Jun 18, 2002·16 cites·6 claims
- 0863US6472336B1Forming an encapsulating layer after deposition of a dielectric comprised of corrosive materialADVANCED MICRO DEVICES INC·Filed 2000·Granted Oct 29, 2002·9 cites·11 claims
- 0955US6989601B1Copper damascene with low-k capping layer and improved electromigration reliabilityADVANCED MICRO DEVICES INC·Filed 2004·Granted Jan 24, 2006·5 cites·8 claims
- 1050US6429141B1Method of manufacturing a semiconductor device with improved line width accuracyADVANCED MICRO DEVICES INC·Filed 2000·Granted Aug 6, 2002·7 cites·8 claims
- 1148US8133801B1Method for forming a semiconducting layer with improved gap filling propertiesSUGINO RINJI·Filed 2005·Granted Mar 13, 2012·0 cites·15 claims
- 1247US6492258B1METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-μM AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBYADVANCED MICRO DEVICES INC·Filed 2001·Granted Dec 10, 2002·3 cites·8 claims
- 1345US6329718B1Method for reducing stress-induced voids for 0.25mμ and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made therebyADVANCED MICRO DEVICES INC·Filed 1998·Granted Dec 11, 2001·12 cites·7 claims
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