Inventor · disambiguated record
Jonathan R. Fales
Also filed as: FALES JONATHAN · FALES JONATHAN R · FALES JONATHAN ROBERT
9 granted patents·1 pending application·28 citations·filing 2004–2021
83Inventor score
Top patents by PatentIndex Score
10 records- 0180US10796067B1EDA CAA with learning phaseCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Oct 6, 2020·2 cites·19 claims
- 0277US11868698B1Context-aware circuit design layout constructCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Jan 9, 2024·1 cites·20 claims
- 0373US7495254B2Test structure and method for detecting and studying crystal lattice dislocation defects in integrated circuit devicesIBM·Filed 2005·Granted Feb 24, 2009·4 cites·20 claims
- 0470US8341564B1Method and system for optimizing migrated implementation of a system designFALES JONATHAN R·Filed 2010·Granted Dec 25, 2012·5 cites·23 claims
- 0569US7984399B1System and method for random defect yield simulation of chip with built-in redundancyCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jul 19, 2011·5 cites·16 claims
- 0656US7194670B2Command multiplier for built-in-self-testIBM·Filed 2004·Granted Mar 20, 2007·9 cites·8 claims
- 0751US11354470B1System and method for device placementCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Jun 7, 2022·0 cites·20 claims
- 0850US7613047B2Efficient circuit and method to measure resistance thresholdsIBM·Filed 2006·Granted Nov 3, 2009·2 cites·17 claims
- 0946US11803684B1Relative placement by application of layered abstractionsCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Oct 31, 2023·0 cites·20 claims
- 1031US2009129185A1Semiconductor circuits capable of self detecting defectsCASSELS JOHN J·Filed 2007·Application pending·0 cites
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