Inventor · disambiguated record
Jeffrey R. Summers
Also filed as: SUMMERS JEFFREY MICHAEL · SUMMERS JEFFREY R · SUMMERS JEFFREY RICHARD
15 granted patents·11 pending applications·164 citations·filing 2000–2011
93Inventor score
Top patents by PatentIndex Score
26 records- 0193US7779232B2Method and apparatus for dynamically managing instruction buffer depths for non-predicted branchesIBM·Filed 2007·Granted Aug 17, 2010·56 cites·20 claims
- 0284US8131976B2Tracking effective addresses in an out-of-order processorDOING RICHARD W·Filed 2009·Granted Mar 6, 2012·18 cites·22 claims
- 0378US8635621B2Method and apparatus to implement software to hardware thread priorityLEVITAN DAVID STEPHEN·Filed 2008·Granted Jan 21, 2014·12 cites·1 claims
- 0478US7934081B2Apparatus and method for using branch prediction heuristics for determination of trace formation readinessIBM·Filed 2006·Granted Apr 26, 2011·8 cites·6 claims
- 0577US7826399B2Structure for preventing starvation in a slotted ring data communications networkIBM·Filed 2008·Granted Nov 2, 2010·7 cites·17 claims
- 0677US7644233B2Apparatus and method for supporting simultaneous storage of trace and standard cache linesIBM·Filed 2006·Granted Jan 5, 2010·8 cites·6 claims
- 0777US6829731B1Method and system for generating a design-specific test case from a generalized set of bus transactionsIBM·Filed 2000·Granted Dec 7, 2004·29 cites·5 claims
- 0873US7996618B2Apparatus and method for using branch prediction heuristics for determination of trace formation readinessIBM·Filed 2011·Granted Aug 9, 2011·3 cites·12 claims
- 0972US7760669B2Method and apparatus for preventing starvation in a slotted ring data communications networkIBM·Filed 2006·Granted Jul 20, 2010·5 cites·14 claims
- 1068US8386712B2Structure for supporting simultaneous storage of trace and standard cache linesIBM·Filed 2008·Granted Feb 26, 2013·4 cites·8 claims
- 1167US8127115B2Group formation with multiple taken branches per groupDOING RICHARD WILLIAM·Filed 2009·Granted Feb 28, 2012·6 cites·30 claims
- 1262US8261276B2Power-efficient thread priority enablementBOSE PRADIP·Filed 2008·Granted Sep 4, 2012·2 cites·16 claims
- 1362US7610449B2Apparatus and method for saving power in a trace cacheIBM·Filed 2006·Granted Oct 27, 2009·2 cites·12 claims
- 1456US7716264B2Method and apparatus for performing alignment shifting in a floating-point unitIBM·Filed 2005·Granted May 11, 2010·2 cites·10 claims
- 1553US7467366B2Method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between componentsIBM·Filed 2006·Granted Dec 16, 2008·2 cites·1 claims
- 1649US2010262813A1Detecting and Handling Short Forward Branch Conversion CandidatesIBM·Filed 2009·Application pending·0 cites
- 1742US2008235500A1Structure for instruction cache trace formationDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 1841US2008250206A1Structure for using branch prediction heuristics for determination of trace formation readinessDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 1941US2008130667A1Distributed arbitration mechanism for ring networksIBM·Filed 2006·Application pending·0 cites
- 2041US2008250207A1Design structure for cache maintenanceDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 2140US2008215804A1Structure for register renaming in a microprocessorDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 2239US2008120468A1Instruction Cache Trace FormationDAVIS GORDON T·Filed 2006·Application pending·0 cites
- 2339US2008077778A1Method and Apparatus for Register Renaming in a MicroprocessorDAVIS GORDON T·Filed 2006·Application pending·0 cites
- 2439US2008114964A1Apparatus and Method for Cache MaintenanceDAVIS GORDON T·Filed 2006·Application pending·0 cites
- 2538US2004167979A1Automatic configuration of metric components in a service level management systemIBM·Filed 2003·Application pending·0 cites
- 2635US2007011222A1Floating-point processor for processing single-precision numbersDANCE SHERMAN M·Filed 2005·Application pending·0 cites
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