Inventor · disambiguated record
Maurizio Bacchetta
Also filed as: BACCHETTA MAURIZIO
10 granted patents·308 citations·filing 1995–2000
92Inventor score
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10 records- 0186US5627403AAdhesion between dielectric layers in an integrated circuitST MICROELECTRONICS SRL·Filed 1995·Granted May 6, 1997·105 cites·12 claims
- 0275US6472750B1Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devicesST MICROELECTRONICS SRL·Filed 2000·Granted Oct 29, 2002·18 cites·13 claims
- 0375US6153537AProcess for the production of a semiconductor device having better interface adhesion between dielectric layersSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Nov 28, 2000·33 cites·22 claims
- 0474US5795821AProcess for improving the interface union among dielectric materials in an integrated circuit manufactureST MICROELECTRONICS SRL·Filed 1996·Granted Aug 18, 1998·45 cites·31 claims
- 0572US6531714B1Process for the production of a semiconductor device having better interface adhesion between dielectric layersSGS THOMSON MICROELECTRONICS·Filed 1998·Granted Mar 11, 2003·28 cites·19 claims
- 0670US5598028AHighly-planar interlayer dielectric thin films in integrated circuitsST MICROELECTRONICS SRL·Filed 1995·Granted Jan 28, 1997·42 cites·16 claims
- 0750US6630739B1Planarization structure and method for dielectric layersST MICROELECTRONICS SRL·Filed 2000·Granted Oct 7, 2003·3 cites·16 claims
- 0850US6239042B1Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devicesSGS THOMSON MICROELECTRONICS·Filed 1997·Granted May 29, 2001·15 cites·39 claims
- 0944US5994231AProcess for depositing a stratified dielectric structure for enhancing the planarity of semiconductor electronic devicesSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Nov 30, 1999·12 cites·8 claims
- 1039US6156637AMethod of planarizing a semiconductor device by depositing a dielectric ply structureST MICROELECTRONICS SRL·Filed 1997·Granted Dec 5, 2000·7 cites·29 claims
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