Inventor · disambiguated record
Swapnil Bahl
Also filed as: BAHL SWAPNIL
13 granted patents·63 citations·filing 2005–2017
90Inventor score
Top patents by PatentIndex Score
13 records- 0190US7353442B2On-chip and at-speed tester for testing and characterization of different types of memoriesST MICROELECTRONICS PVT LTD·Filed 2005·Granted Apr 1, 2008·20 cites·20 claims
- 0283US8381051B2Testing of multi-clock domainsST MICROELECTRONICS INT NV·Filed 2010·Granted Feb 19, 2013·5 cites·15 claims
- 0382US8527824B2Testing of multi-clock domainsST MICROELECTRONICS INT NV·Filed 2013·Granted Sep 3, 2013·4 cites·5 claims
- 0482US7814385B2Self programmable shared bist for testing multiple memoriesST MICROELECTRONICS PVT LTD·Filed 2007·Granted Oct 12, 2010·13 cites·17 claims
- 0579US9234938B2Monitoring on-chip clock control during integrated circuit testingST MICROELECTRONICS INT NV·Filed 2014·Granted Jan 12, 2016·4 cites·21 claims
- 0674US8917123B2Integrated circuit with reduced power consumption in a test mode, and related methodsST MICROELECTRONICS INT NV·Filed 2013·Granted Dec 23, 2014·4 cites·20 claims
- 0766US9264049B2Synchronous on-chip clock controllersST MICROELECTRONICS INT NV·Filed 2013·Granted Feb 16, 2016·2 cites·22 claims
- 0864US9606180B2Scan compression architecture for highly compressed designs and associated methodsST MICROELECTRONICS INT NV·Filed 2014·Granted Mar 28, 2017·1 cites·16 claims
- 0964US8775857B2Sequential on-chip clock controller with dynamic bypass for multi-clock domain testingKHULLAR SHRAY·Filed 2011·Granted Jul 8, 2014·3 cites·20 claims
- 1058US7321520B2Configurable length first-in first-out memoryST MICROELECTRONICS PVT LTD·Filed 2006·Granted Jan 22, 2008·1 cites·19 claims
- 1156US8458545B2Method and apparatus for testing of a memory with redundancy elementsROY TANMOY·Filed 2010·Granted Jun 4, 2013·3 cites·31 claims
- 1256US7372755B2On-chip storage memory for storing variable data bitsST MICROELECTRONICS PVT LTD·Filed 2005·Granted May 13, 2008·3 cites·25 claims
- 1341US10354742B2Scan compression architecture for highly compressed designs and associated methodsST MICROELECTRONICS INT NV·Filed 2017·Granted Jul 16, 2019·0 cites·20 claims
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