Inventor · disambiguated record
Michael Laor
Also filed as: LAOR MICHAEL
20 granted patents·1 pending application·1,585 citations·filing 1995–2015
97Inventor score
Files withCISCO TECH IND9CISCO TECH INC6COMPASS ELECTRO OPTICAL SYSTEMS LTD2MESH MICHAEL2EPPS GARRY P1
Top patents by PatentIndex Score
21 records- 0198US6977930B1Pipelined packet switching and queuing architectureCISCO TECH IND·Filed 2000·Granted Dec 20, 2005·193 cites·37 claims
- 0297US7643486B2Pipelined packet switching and queuing architectureCISCO TECH INC·Filed 2005·Granted Jan 5, 2010·86 cites·46 claims
- 0397US6980552B1Pipelined packet switching and queuing architectureCISCO TECH IND·Filed 2002·Granted Dec 27, 2005·196 cites·33 claims
- 0497US6721316B1Flexible engine and data structure for packet header processingCISCO TECH IND·Filed 2000·Granted Apr 13, 2004·207 cites·24 claims
- 0596US8392487B1Programmable matrix processorMESH MICHAEL·Filed 2008·Granted Mar 5, 2013·98 cites·16 claims
- 0696US6813243B1High-speed hardware implementation of red congestion control algorithmCISCO TECH IND·Filed 2000·Granted Nov 2, 2004·142 cites·18 claims
- 0796US6778546B1High-speed hardware implementation of MDRR algorithm over a large number of queuesCISCO TECH IND·Filed 2000·Granted Aug 17, 2004·169 cites·23 claims
- 0894US6831923B1Pipelined multiple issue packet switchCISCO TECH IND·Filed 2000·Granted Dec 14, 2004·103 cites·8 claims
- 0993US8018937B2Pipelined packet switching and queuing architectureCISCO TECH INC·Filed 2005·Granted Sep 13, 2011·21 cites·32 claims
- 1093US6731644B1Flexible DMA engine for packet header modificationCISCO TECH IND·Filed 2000·Granted May 4, 2004·99 cites·17 claims
- 1183US8325403B1Optical programmable matrix processorMESH MICHAEL·Filed 2009·Granted Dec 4, 2012·7 cites·16 claims
- 1283US6147996APipelined multiple issue packet switchCISCO TECH IND·Filed 1995·Granted Nov 14, 2000·124 cites·40 claims
- 1381US7675926B2Hierarchical QoS behavioral modelCISCO TECH INC·Filed 2004·Granted Mar 9, 2010·35 cites·27 claims
- 1480US8665875B2Pipelined packet switching and queuing architectureEPPS GARRY P·Filed 2011·Granted Mar 4, 2014·5 cites·20 claims
- 1580US7554907B1High-speed hardware implementation of RED congestion control algorithmCISCO TECH INC·Filed 2004·Granted Jun 30, 2009·24 cites·50 claims
- 1679US7304999B2Methods and apparatus for processing packets including distributing packets across multiple packet processing engines and gathering the processed packets from the processing enginesCISCO TECH INC·Filed 2002·Granted Dec 4, 2007·27 cites·34 claims
- 1769US9363173B2Router and switch architectureLAOR MICHAEL·Filed 2011·Granted Jun 7, 2016·4 cites·12 claims
- 1868US7286525B1Synchronous pipelined switch using serial transmissionCISCO TECH INC·Filed 2002·Granted Oct 23, 2007·10 cites·53 claims
- 1958US6424649B1Synchronous pipelined switch using serial transmissionCISCO TECH IND·Filed 1997·Granted Jul 23, 2002·35 cites·11 claims
- 2051US9304272B2EO device for processing data signalsCOMPASS ELECTRO OPTICAL SYSTEMS LTD·Filed 2013·Granted Apr 5, 2016·0 cites·13 claims
- 2135US2017111294A1Integrated folded clos architectureCOMPASS ELECTRO OPTICAL SYSTEMS LTD·Filed 2015·Application pending·0 cites
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