Inventor · disambiguated record
Luciano Lavagno
Also filed as: LAVAGNO LUCIANO
18 granted patents·1 pending application·223 citations·filing 1995–2023
94Inventor score
Files withCADENCE DESIGN SYSTEMS INC9CORTADELLA JORDI3XILINX INC3CADENCE DESIGN SYSTEM INC1INST OF COMP SCIENCE FOUNDATION FOR RES AND TECHNOLOGY HELLAS1
Top patents by PatentIndex Score
19 records- 0189US8572539B2Variability-aware scheme for high-performance asynchronous circuit voltage regulationCORTADELLA JORDI·Filed 2008·Granted Oct 29, 2013·24 cites·13 claims
- 0289US7587687B2System and method for incremental synthesisCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Sep 8, 2009·23 cites·10 claims
- 0387US8446224B2Network of tightly coupled performance monitors for determining the maximum frequency of operation of a semiconductor ICCORTADELLA JORDI·Filed 2011·Granted May 21, 2013·13 cites·17 claims
- 0486US7634749B1Skew insensitive clocking method and apparatusCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Dec 15, 2009·18 cites·18 claims
- 0580US7870516B2Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the sameINST OF COMP SCIENCE FOUNDATION FOR RES AND TECHNOLOGY HELLAS·Filed 2007·Granted Jan 11, 2011·10 cites·11 claims
- 0679US7702499B1Systems and methods for performing software performance estimationsCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Apr 20, 2010·39 cites·52 claims
- 0778US7069204B1Method and system for performance level modeling and simulation of electronic systems having both hardware and software elementsCADENCE DESIGN SYSTEM INC·Filed 2000·Granted Jun 27, 2006·44 cites·29 claims
- 0876US8433875B2Asynchronous scheme for clock domain crossingCORTADELLA JORDI·Filed 2010·Granted Apr 30, 2013·7 cites·14 claims
- 0976US7873948B2Method and system for split-compiling a hybrid language programCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jan 18, 2011·7 cites·20 claims
- 1073US7472361B2System and method for generating a plurality of models at different levels of abstraction from a single master modelCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Dec 30, 2008·7 cites·19 claims
- 1158US7673259B2System and method for synthesis reuseCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Mar 2, 2010·1 cites·27 claims
- 1253US2025156617A1Simulating data transfers for high-level synthesis designsXILINX INC·Filed 2023·Application pending·0 cites
- 1350US12468581B2Inter-kernel dataflow analysis and deadlock detectionXILINX INC·Filed 2021·Granted Nov 11, 2025·0 cites·16 claims
- 1448US8286108B2System and method for synthesis reuseLAVAGNO LUCIANO·Filed 2009·Granted Oct 9, 2012·0 cites·24 claims
- 1547US11520570B1Application-specific hardware pipeline implemented in an integrated circuitXILINX INC·Filed 2021·Granted Dec 6, 2022·0 cites·18 claims
- 1645US7010784B1Method and system for split-compiling a hybrid language programCADENCE DESIGN SYSTEMS INC·Filed 1999·Granted Mar 7, 2006·15 cites·46 claims
- 1738US5682519AMethod for reducing power consumption of switching nodes in a circuitCADENCE DESIGN SYSTEMS INC·Filed 1995·Granted Oct 28, 1997·11 cites·19 claims
- 1836US11048008B2Capacitive sensor and method for sensing changes in a spaceSISVEL TECH S R L·Filed 2017·Granted Jun 29, 2021·0 cites·16 claims
- 1931US5696692AConditional selection method for reducing power consumption in a circuitCADENCE DESIGN SYSTEMS INC·Filed 1995·Granted Dec 9, 1997·4 cites·32 claims
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