Inventor · disambiguated record
Kevin X. Zhang
Also filed as: ZHANG KEVIN · ZHANG KEVIN X · ZHANG KEVIN XIAOQIANG
55 granted patents·6 pending applications·861 citations·filing 1996–2019
99Inventor score
Files withINTEL CORP43HEWLETT PACKARD CO4CHEN ZHANPING2TAIWAN SEMICONDUCTOR MFG CO LTD2TONG XIANGHONG2
Top patents by PatentIndex Score
61 records- 0194US7403426B2Memory with dynamically adjustable supplyINTEL CORP·Filed 2005·Granted Jul 22, 2008·36 cites·12 claims
- 0292US8519462B26F2 DRAM cellWANG YIH·Filed 2011·Granted Aug 27, 2013·20 cites·11 claims
- 0390US5986923AMethod and apparatus for improving read/write stability of a single-port SRAM cellHEWLETT PACKARD CO·Filed 1998·Granted Nov 16, 1999·97 cites·8 claims
- 0488US8451670B2Adaptive and dynamic stability enhancement for memoriesKOLAR PRAMOD·Filed 2010·Granted May 28, 2013·14 cites·20 claims
- 0587US7079426B2Dynamic multi-Vcc scheme for SRAM cell stability controlINTEL CORP·Filed 2004·Granted Jul 18, 2006·46 cites·20 claims
- 0686US6181608B1Dual Vt SRAM cell with bitline leakage controlINTEL CORP·Filed 1999·Granted Jan 30, 2001·62 cites·24 claims
- 0785US6518826B2Method and apparatus for dynamic leakage controlINTEL CORP·Filed 2001·Granted Feb 11, 2003·36 cites·35 claims
- 0882US5815432ASingle-ended read, dual-ended write SCRAM cellHEWLETT PACKARD CO·Filed 1997·Granted Sep 29, 1998·51 cites·8 claims
- 0979US6026011ACMOS latch design with soft error immunityINTEL CORP·Filed 1998·Granted Feb 15, 2000·42 cites·16 claims
- 1078US8406073B1Hierarchical DRAM sensingSOMASEKHAR DINESH·Filed 2010·Granted Mar 26, 2013·8 cites·19 claims
- 1177US6292401B1Method and apparatus for global bitline multiplexing for a high-speed memoryINTEL CORP·Filed 2000·Granted Sep 18, 2001·23 cites·15 claims
- 1277US6198656B1Asymmetric memory cell for single-ended sensingINTEL CORP·Filed 1999·Granted Mar 6, 2001·37 cites·10 claims
- 1376US7177176B2Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strengthINTEL CORP·Filed 2004·Granted Feb 13, 2007·23 cites·8 claims
- 1476US6862207B2Static random access memoryINTEL CORP·Filed 2002·Granted Mar 1, 2005·21 cites·34 claims
- 1574US7981756B2Common plate capacitor array connections, and processes of making sameINTEL CORP·Filed 2008·Granted Jul 19, 2011·5 cites·22 claims
- 1674US6442089B1Multi-level, low voltage swing sensing scheme for high speed memory designINTEL CORP·Filed 1999·Granted Aug 27, 2002·33 cites·27 claims
- 1773US8395923B2Antifuse programmable memory arrayCHEN ZHANPING·Filed 2009·Granted Mar 12, 2013·10 cites·23 claims
- 1873US6948079B2Method and apparatus for providing supply voltages for a processorINTEL CORP·Filed 2001·Granted Sep 20, 2005·19 cites·14 claims
- 1972US7657767B2Cache leakage shut-off mechanismINTEL CORP·Filed 2005·Granted Feb 2, 2010·7 cites·23 claims
- 2072US6038693AError correction scheme for an integrated L2 cacheINTEL CORP·Filed 1998·Granted Mar 14, 2000·59 cites·9 claims
- 2170US10878872B2Random access memoryTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 29, 2020·2 cites·20 claims
- 2269US5949256AAsymmetric sense amplifier for single-ended memory arraysHEWLETT PACKARD CO·Filed 1997·Granted Sep 7, 1999·38 cites·20 claims
- 2363US8242831B2Tamper resistant fuse designTONG XIANGHONG·Filed 2009·Granted Aug 14, 2012·3 cites·20 claims
- 2461US9123724B2Methods of forming secured metal gate antifuse structuresINTEL CORP·Filed 2013·Granted Sep 1, 2015·1 cites·9 claims
- 2561US6255861B1Hybrid low voltage swing sense amplifierINTEL CORP·Filed 1999·Granted Jul 3, 2001·16 cites·27 claims
- 2660US6992405B2Dynamic voltage scaling scheme for an on-die voltage differentiator designINTEL CORP·Filed 2002·Granted Jan 31, 2006·9 cites·23 claims
- 2760US6707752B2Tag design for cache access with redundant-form addressINTEL CORP·Filed 2001·Granted Mar 16, 2004·11 cites·21 claims
- 2858US7417913B2Fuse cell having adjustable sensing marginINTEL CORP·Filed 2006·Granted Aug 26, 2008·4 cites·23 claims
- 2958US7230842B2Memory cell having p-type pass deviceINTEL CORP·Filed 2005·Granted Jun 12, 2007·5 cites·20 claims
- 3058US6282143B1Multi-port static random access memory design for column interleaved arraysHEWLETT PACKARD CO·Filed 1998·Granted Aug 28, 2001·18 cites·22 claims
- 3157US8618613B2Methods of forming secured metal gate antifuse structuresTONG XIANGHONG·Filed 2011·Granted Dec 31, 2013·1 cites·19 claims
- 3257US8411482B2Programmable read only memoryCHEN ZHANPING·Filed 2008·Granted Apr 2, 2013·4 cites·24 claims
- 3355US6621726B2Biasing technique for a high density SRAMINTEL CORP·Filed 2001·Granted Sep 16, 2003·7 cites·22 claims
- 3454US7089360B1Shared cache wordline decoder for redundant and regular addressesINTEL CORP·Filed 2000·Granted Aug 8, 2006·3 cites·33 claims
- 3553US6483375B1Low power operation mechanism and methodINTEL CORP·Filed 2001·Granted Nov 19, 2002·6 cites·30 claims
- 3652US7924596B2Area efficient programmable read only memory (PROM) arrayINTEL CORP·Filed 2007·Granted Apr 12, 2011·2 cites·21 claims
- 3752US6982500B2Power-down scheme for an on-die voltage differentiator designINTEL CORP·Filed 2002·Granted Jan 3, 2006·2 cites·17 claims
- 3850US9013941B2DRAM with pulse sense ampINTEL CORP·Filed 2013·Granted Apr 21, 2015·1 cites·15 claims
- 3950US6407589B1Device for current sensing in an amplifier with PMOS voltage conversionINTEL CORP·Filed 2000·Granted Jun 18, 2002·6 cites·17 claims
- 4049US5694362AMethod and apparatus for high speed comparisonIBM·Filed 1996·Granted Dec 2, 1997·12 cites·20 claims
- 4148US6775181B2Biasing technique for a high density SRAMINTEL CORP·Filed 2003·Granted Aug 10, 2004·7 cites·22 claims
- 4247US6330182B1Method for evaluating soft error immunity of CMOS circuitsINTEL CORP·Filed 1998·Granted Dec 11, 2001·10 cites·15 claims
- 4347US6204698B1Robust low voltage swing sense amplifierINTEL CORP·Filed 1999·Granted Mar 20, 2001·10 cites·21 claims
- 4446US6507531B1Cache column multiplexing using redundant form addressesINTEL CORP·Filed 2000·Granted Jan 14, 2003·4 cites·27 claims
- 4545US6650171B2Low power operation mechanism and methodINTEL CORP·Filed 2002·Granted Nov 18, 2003·3 cites·24 claims
- 4643US7337372B2Method and apparatus for detecting multi-hit errors in a cacheINTEL CORP·Filed 2003·Granted Feb 26, 2008·0 cites·7 claims
- 4742US6862225B2Buffer for a split cache line accessINTEL CORP·Filed 2004·Granted Mar 1, 2005·2 cites·17 claims
- 4841US8982659B2Bitline floating during non-access mode for memory arraysCHANG TSUNG-YUNG·Filed 2009·Granted Mar 17, 2015·2 cites·20 claims
- 4941US2003126477A1Method and apparatus for controlling a supply voltage to a processorFiled 2001·Application pending·0 cites
- 5040US6622267B1Method and apparatus for detecting multi-hit errors in cacheINTEL CORP·Filed 1999·Granted Sep 16, 2003·10 cites·5 claims
Showing the top 50 of 61 patent records by PatentIndex Score.
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