Inventor · disambiguated record
Venugopal Boynapalli
Also filed as: BOYNAPALLI VENUGOPAL
32 granted patents·11 pending applications·84 citations·filing 2010–2023
95Inventor score
Top patents by PatentIndex Score
43 records- 0197US9831272B2Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenchesQUALCOMM INC·Filed 2016·Granted Nov 28, 2017·26 cites·30 claims
- 0295US11710733B2Vertical power grid standard cell architectureQUALCOMM INC·Filed 2020·Granted Jul 25, 2023·4 cites·12 claims
- 0391US10103626B1Digital power multiplexorQUALCOMM INC·Filed 2017·Granted Oct 16, 2018·9 cites·18 claims
- 0488US9755618B1Low-area low clock-power flip-flopQUALCOMM INC·Filed 2016·Granted Sep 5, 2017·7 cites·19 claims
- 0587US10038429B1High-speed soft-edge sense-amplifier-based flip-flopQUALCOMM INC·Filed 2017·Granted Jul 31, 2018·6 cites·22 claims
- 0686US9979381B1Semi-data gated flop with low clock power/low internal power with minimal area overheadQUALCOMM INC·Filed 2016·Granted May 22, 2018·5 cites·22 claims
- 0781US10600866B2Standard cell architecture for gate tie-offQUALCOMM INC·Filed 2018·Granted Mar 24, 2020·2 cites·12 claims
- 0880US10777640B2Standard cell architecture for gate tie-offQUALCOMM INC·Filed 2020·Granted Sep 15, 2020·1 cites·23 claims
- 0980US9230691B1Shared repair register for memory redundancyQUALCOMM INC·Filed 2014·Granted Jan 5, 2016·7 cites·27 claims
- 1075US9990984B1Pulse-stretcher clock generator circuit for high speed memory subsystemsQUALCOMM INC·Filed 2016·Granted Jun 5, 2018·2 cites·14 claims
- 1174US9577639B1Source separated cellQUALCOMM INC·Filed 2015·Granted Feb 21, 2017·3 cites·30 claims
- 1272US9960231B2Standard cell architecture for parasitic resistance reductionQUALCOMM INC·Filed 2016·Granted May 1, 2018·2 cites·20 claims
- 1370US10490543B2Placement methodology to remove fillerQUALCOMM INC·Filed 2017·Granted Nov 26, 2019·1 cites·13 claims
- 1470US9806717B2High-speed level-shifting multiplexerQUALCOMM INC·Filed 2016·Granted Oct 31, 2017·2 cites·7 claims
- 1568US10236886B2Multiple via structure for high performance standard cellsQUALCOMM INC·Filed 2016·Granted Mar 19, 2019·1 cites·12 claims
- 1667US10784345B2Standard cell architecture for gate tie-offQUALCOMM INC·Filed 2020·Granted Sep 22, 2020·0 cites·19 claims
- 1765US12431877B2Hybrid flop tray including different fin size flip-flopsQUALCOMM INC·Filed 2023·Granted Sep 30, 2025·0 cites·19 claims
- 1865US11133803B2Multiple via structure for high performance standard cellsQUALCOMM INC·Filed 2020·Granted Sep 28, 2021·0 cites·20 claims
- 1964US9490813B2High-speed level-shifting multiplexerQUALCOMM INC·Filed 2014·Granted Nov 8, 2016·2 cites·27 claims
- 2064US9071239B2Method and semiconductor apparatus for reducing power when transmitting data between devices in the semiconductor apparatusQUALCOMM INC·Filed 2013·Granted Jun 30, 2015·2 cites·36 claims
- 2161US9189438B2Method and apparatus for dynamic power saving with flexible gating in a cross-bar architectureQUALCOMM INC·Filed 2013·Granted Nov 17, 2015·1 cites·7 claims
- 2259US11237580B1Systems and methods providing leakage reduction for power gated domainsQUALCOMM INC·Filed 2020·Granted Feb 1, 2022·0 cites·21 claims
- 2359US9979394B2Pulse-generatorQUALCOMM INC·Filed 2016·Granted May 22, 2018·1 cites·16 claims
- 2458US10965289B2Metal oxide semiconductor device of an integrated circuitQUALCOMM INC·Filed 2019·Granted Mar 30, 2021·0 cites·8 claims
- 2554US12334143B2Power level comparator with switching inputQUALCOMM INC·Filed 2023·Granted Jun 17, 2025·0 cites·24 claims
- 2654US12323142B2Integrated power management cells for gate all around technologiesQUALCOMM INC·Filed 2023·Granted Jun 3, 2025·0 cites·19 claims
- 2751US2024170488A1Integrated circuit cell including column stacked pinsQUALCOMM INC·Filed 2022·Application pending·0 cites
- 2850US11361817B2Pseudo-triple-port SRAM bitcell architectureQUALCOMM INC·Filed 2020·Granted Jun 14, 2022·0 cites·25 claims
- 2950US2024266342A1Column divided multi-height architectureQUALCOMM INC·Filed 2023·Application pending·0 cites
- 3050US2024249056A1Engineering change order (eco) spare cellQUALCOMM INC·Filed 2023·Application pending·0 cites
- 3149US11437379B2Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuitsQUALCOMM INC·Filed 2020·Granted Sep 6, 2022·0 cites·21 claims
- 3249US11290109B1Multibit multi-height cell to improve pin accessibilityQUALCOMM INC·Filed 2020·Granted Mar 29, 2022·0 cites·18 claims
- 3349US2013246681A1Power gating for high speed xbar architectureRAO HARI M·Filed 2012·Application pending·0 cites
- 3446US2022115405A1Heterogeneous height logic cell architectureQUALCOMM INC·Filed 2020·Application pending·0 cites
- 3543US9081060B2Buffer testing for reconfigurable instruction cell arraysQUALCOMM INC·Filed 2013·Granted Jul 14, 2015·0 cites·16 claims
- 3643US2016004617A1Automatic test pattern generation for a reconfigurable instruction cell arrayQUALCOMM INC·Filed 2014·Application pending·0 cites
- 3741US2024322819A1Fine grain power gatingQUALCOMM INC·Filed 2023·Application pending·0 cites
- 3840US10692808B2High performance cell design in a technology with high density metal routingQUALCOMM INC·Filed 2017·Granted Jun 23, 2020·0 cites·13 claims
- 3938US2019252408A1Staggered self aligned gate contactQUALCOMM INC·Filed 2018·Application pending·0 cites
- 4038US2020335151A1Low-power memoryQUALCOMM INC·Filed 2020·Application pending·0 cites
- 4135US2018167058A1Clock gating cell for low setup time for high frequency designsQUALCOMM INC·Filed 2016·Application pending·0 cites
- 4234US9666301B2Scannable memories with robust clocking methodology to prevent inadvertent reads or writesQUALCOMM INC·Filed 2014·Granted May 30, 2017·0 cites·28 claims
- 4331US2011219266A1System and Method of Testing an Error Correction ModuleQUALCOMM INC·Filed 2010·Application pending·0 cites
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