Inventor · disambiguated record
Kei-Yong Khoo
Also filed as: KHOO KEI Y · KHOO KEI-YONG
10 granted patents·83 citations·filing 1993–2012
88Inventor score
Top patents by PatentIndex Score
10 records- 0182US7669165B2Method and system for equivalence checking of a low power designCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 23, 2010·16 cites·20 claims
- 0279US8875087B1Method and system for automated script generation for EDA toolsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Oct 28, 2014·6 cites·39 claims
- 0378US7373618B1Method and system for selection and replacement of subcircuits in equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted May 13, 2008·12 cites·33 claims
- 0476US5479363AProgrammable digital signal processor using switchable unit-delays for optimal hardware allocationUNIV CALIFORNIA·Filed 1993·Granted Dec 26, 1995·29 cites·10 claims
- 0567US7266790B2Method and system for logic equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Sep 4, 2007·10 cites·44 claims
- 0661US7627842B1Method and system for verification of circuits with encoded signalsCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Dec 1, 2009·8 cites·49 claims
- 0758US7735035B1Method and system for creating a boolean model of multi-path and multi-strength signals for verificationCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 8, 2010·1 cites·23 claims
- 0852US8132135B2Method and system for creating a boolean model of multi-path and multi-strength signals for verificationKHOO KEI-YONG·Filed 2008·Granted Mar 6, 2012·1 cites·19 claims
- 0948US7620919B2Method and system for logic equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Nov 17, 2009·0 cites·17 claims
- 1048US7620918B2Method and system for logic equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Nov 17, 2009·0 cites·25 claims
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