Inventor · disambiguated record
Eitan Cadouri
Also filed as: CADOURI EITAN
16 granted patents·1 pending application·301 citations·filing 2003–2011
92Inventor score
Top patents by PatentIndex Score
17 records- 0197US6826738B2Optimization of die placement on wafersPDF SOLUTIONS INC·Filed 2003·Granted Nov 30, 2004·213 cites·18 claims
- 0286US7555736B2Method and system for using pattern matching to process an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 30, 2009·12 cites·16 claims
- 0385US7913206B1Method and mechanism for performing partitioning of DRC operationsCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Mar 22, 2011·17 cites·30 claims
- 0483US7657856B1Method and system for parallel processing of IC design layoutsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 2, 2010·15 cites·28 claims
- 0582US7904852B1Method and system for implementing parallel processing of electronic design automation toolsCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Mar 8, 2011·20 cites·60 claims
- 0674US7908579B2Method and mechanism for extraction and recognition of polygons in an IC designCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Mar 15, 2011·5 cites·35 claims
- 0773US7039543B1Transforming yield information of a semiconductor fabrication processPDF SOLUTIONS INC·Filed 2004·Granted May 2, 2006·6 cites·20 claims
- 0863US7508071B2Adjusting die placement on a semiconductor wafer to increase yieldPDF SOLUTIONS INC·Filed 2006·Granted Mar 24, 2009·1 cites·20 claims
- 0963US7220605B1Selecting dice to test using a yield mapPDF SOLUTIONS INC·Filed 2004·Granted May 22, 2007·7 cites·40 claims
- 1061US7617465B1Method and mechanism for performing latch-up check on an IC designCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Nov 10, 2009·2 cites·30 claims
- 1156US8429588B2Method and mechanism for extraction and recognition of polygons in an IC designIRMATOV ANWAR·Filed 2011·Granted Apr 23, 2013·1 cites·18 claims
- 1247US7440869B1Mapping yield information of semiconductor dicePDF SOLUTIONS INC·Filed 2004·Granted Oct 21, 2008·1 cites·45 claims
- 1347US7169638B1Adjusting die placement on a semiconductor wafer to increase yieldPDF SOLUTIONS INC·Filed 2004·Granted Jan 30, 2007·1 cites·22 claims
- 1444US7334205B1Optimization of die placement on wafersPDF SOLUTIONS INC·Filed 2004·Granted Feb 19, 2008·0 cites·20 claims
- 1538US2006278956A1Semiconductor wafer with non-rectangular shaped dicePDF SOLUTIONS INC·Filed 2004·Application pending·0 cites
- 1637US7190183B1Selecting die placement on a semiconductor wafer to reduce test timePDF SOLUTIONS INC·Filed 2004·Granted Mar 13, 2007·0 cites·16 claims
- 1736US7418682B1Method and mechanism for performing DRC processing with reduced passes through an IC designCADENCE DESIGN SYSYEMS INC·Filed 2005·Granted Aug 26, 2008·0 cites·21 claims
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