Inventor · disambiguated record
Arvind Nembili Veeravalli
Also filed as: VEERAVALLI ARVIND NEMBILI
7 granted patents·31 citations·filing 2008–2022
80Inventor score
Technology areasG06F
Top patents by PatentIndex Score
7 records- 0190US9881123B1Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impactCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 30, 2018·12 cites·20 claims
- 0288US10114920B1Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logicCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 30, 2018·8 cites·20 claims
- 0384US11455450B1System and method for performing sign-off timing analysis of electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Sep 27, 2022·2 cites·13 claims
- 0467US8255850B2Fabricating IC with NBTI path delay within timing constraintsJAIN PALKESH·Filed 2009·Granted Aug 28, 2012·5 cites·2 claims
- 0562US8051399B2IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing analysisTEXAS INSTRUMENTS INC·Filed 2008·Granted Nov 1, 2011·4 cites·7 claims
- 0656US12332304B1System and method for automatic fault detection in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Jun 17, 2025·0 cites·20 claims
- 0750US12475286B1System and method for comparing circuit design constraint setsCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Nov 18, 2025·0 cites·20 claims
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