Inventor

BASTOS RUI M

US62 patents

⚠️ This page may combine multiple inventors who share the name “BASTOS RUI M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BASTOS RUI M

NVIDIA CORP

Method and apparatus for multithreaded processing of data in a programmable graphics processor

Generation of jittered sub-pixel samples using programmable sub-pixel offsets

Order-independent transparency rendering system and method

System and method for using and collecting information from a plurality of depth layers

System and method for dual-depth shadow-mapping

Systems and methods of multi-pass data processing

Antialiasing using hybrid supersampling-multisampling

Temporal antialiasing in a multisampling graphics pipeline

System and method for reserving and managing memory spaces in a memory resource

Method and apparatus for processing stencil data using a programmable graphics processor

Multiple data buffers for processing graphics data

Generation of jittered sub-pixel samples using programmable sub-pixel offsets

System, method and computer program product for providing arbitrary texture filtering

Methods of processing graphics data including reading and writing buffers

Position conflict detection and avoidance in a programmable graphics processor

Multiple data buffers for processing graphics data

Shader pixel storage in a graphics memory

Programmable shader having register forwarding for reduced register-file bandwidth consumption

Dynamic texture fetch cancellation

Antialiasing using hybrid supersampling-multisampling

Graphical shader by using delay

System and method for synchronizing divergent samples in a programmable graphics processing unit

Perspective correction computation optimization

Increased scalability in the fragment shading pipeline

Scalable shader architecture

Depth-of-field effects using texture lookup

Translation of register-combiner state into shader microcode

Fragment processor having dual mode register file

Scheduling program instruction execution by using fence instructions

Fragment scattering

Apparatus, system, and method for increased processing flexibility of a graphic pipeline

System and method for processing divergent samples in a programmable graphics processing unit

Per-fragment control for writing an output buffer

Subpicture overlay using fragment shader

Digital image compositing using a programmable graphics processor

Method and system for texture instruction demotion optimization

Optional color space conversion

Architecture for compact multi-ported register file

Shader with cache memory

Digital image compositing using a programmable graphics processor

Methods of processing graphics data including reading and writing buffers

Pixel center position displacement

Target independent rasterization with multiple color samples

Rendering using multiple render target sample masks

Pixel shader bypass for low power graphics rendering

Digital image compositing using a programmable graphics processor

Partial texture loads

Divergent and non-divergent texture fetches

Partial texture loads

EVERITT CASS W

Temporal antialiasing in a multisampling graphics pipeline