Inventor

NICKOLLS JOHN R

US66 patents

⚠️ This page may combine multiple inventors who share the name “NICKOLLS JOHN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NICKOLLS JOHN R

NVIDIA CORP

Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior

Synchronization of threads in a cooperative thread array

Structured programming control flow in a SIMD architecture

Single interconnect providing read and write access to a memory shared by concurrent threads

Counter-based delay of dependent thread group execution

Atomic memory operators in a parallel processor

Processing an indirect branch instruction in a SIMD architecture

Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue

Methods for scalably exploiting parallelism in a parallel processing system

Apparatus and method for monitoring and debugging a graphics processing unit

Defect tolerant redundancy

Lock mechanism to enable atomic updates to shared memory

Apparatus and method for debugging a graphics processing unit in response to a debug instruction

Register file allocation

Simulating multiported memories using lower port count memories

Register based queuing for texture requests

Fast fourier transforms and related transforms using cooperative thread arrays

Bit reversal methods for a parallel processor

Instructions for managing a parallel cache hierarchy

Indirect function call instructions in a synchronous parallel thread processor

Lock mechanism to enable atomic updates to shared memory

Distributing processing tasks within a processor

Generating event signals for performance register control using non-operative instructions

NICKOLLS JOHN R

Virtual architecture and instruction set for parallel thread computing

Architecture and instructions for accessing multi-dimensional formatted surface memory

Parallel data processing systems and methods using cooperative thread arrays with unique thread identifiers as an input to compute an identifier of a location in a shared memory

Coalescing memory barrier operations across multiple parallel threads

Unified addressing and instructions for accessing parallel memory spaces

Unanimous branch instructions in a parallel thread processor

Systems and methods for voting among parallel threads

MASPAR COMPUTER CORP

Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount

Input/output system for parallel processing arrays

Scalable processor to processor and processor to I/O interconnection network and method for parallel processing arrays

Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays

Parallel processor memory transfer system using parallel transfers between processors and staging registers and sequential transfers between staging registers and memory

COON BRETT W

Shared memory with parallel access and access conflict resolution mechanism

Thread group scheduler for computing on a parallel thread processor

Indirect function call instructions in a synchronous parallel thread processor

Shared single-access memory with management of multiple parallel requests

BROADCOM CORP

Galois field arithmetic unit for use within a processor

Reconfigurable processing system and method

Galois field multiplier array for use within a finite field arithmetic unit

Processor having a finite field arithmetic unit utilizing an array of multipliers and adders

NYLAND LARS

Systems and methods for coalescing memory accesses of parallel threads

Systems and methods for coalescing memory accesses of parallel threads

SHEBANOW MICHAEL C

Address mapping for a parallel thread processor

Trap handler architecture for a parallel processing unit

HEINRICH STEVEN JAMES

Cache operations and policies for a multi-threaded client

MASPAR COMPUTER CO

Broadcasting headers to configure physical devices interfacing a data bus with a logical assignment and to effect block data transfers between the configured logical devices

FAHS BRIAN

Efficient implementation of arrays of structures on SIMT and SIMD architectures