Inventor · disambiguated record
Jiong-Ping Lu
Also filed as: LU JIONG · LU JIONG-PING
67 granted patents·22 pending applications·1,605 citations·filing 1997–2019
99Inventor score
Top patents by PatentIndex Score
89 records- 0199US6017818AProcess for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect densityTEXAS INSTRUMENTS INC·Filed 1997·Granted Jan 25, 2000·650 cites·12 claims
- 0298US7544987B2High-k dielectric materials and processes for manufacturing themMICRON TECHNOLOGY INC·Filed 2005·Granted Jun 9, 2009·59 cites·8 claims
- 0390US6451646B1High-k dielectric materials and processes for manufacturing themMICRON TECHNOLOGY INC·Filed 2000·Granted Sep 17, 2002·32 cites·16 claims
- 0490US6008540AIntegrated circuit dielectric and methodTEXAS INSTRUMENTS INC·Filed 1998·Granted Dec 28, 1999·81 cites·2 claims
- 0589US6624066B2Reliable interconnects with low via/contact resistanceTEXAS INSTRUMENTS INC·Filed 2001·Granted Sep 23, 2003·83 cites·3 claims
- 0688US5913145AMethod for fabricating thermally stable contacts with a diffusion barrier formed at high temperaturesTEXAS INSTRUMENTS INC·Filed 1997·Granted Jun 15, 1999·92 cites·13 claims
- 0786US7422967B2Method for manufacturing a semiconductor device containing metal silicide regionsTEXAS INSTRUMENTS INC·Filed 2005·Granted Sep 9, 2008·15 cites·13 claims
- 0884US6100188AStable and low resistance metal/barrier/silicon stack structure and related process for manufacturingTEXAS INSTRUMENTS INC·Filed 1998·Granted Aug 8, 2000·55 cites·27 claims
- 0983US6187656B1CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodesTEXAS INSTRUMENTS INC·Filed 1998·Granted Feb 13, 2001·58 cites·24 claims
- 1081US6265303B1Integrated circuit dielectric and methodTEXAS INSTRUMENTS INC·Filed 1999·Granted Jul 24, 2001·46 cites·4 claims
- 1180US6184129B1Low resistivity poly-silicon gate produced by selective metal growthTEXAS INSTRUMENTS INC·Filed 1999·Granted Feb 6, 2001·43 cites·20 claims
- 1276US6743719B1Method for forming a conductive copper structureTEXAS INSTRUMENTS INC·Filed 2003·Granted Jun 1, 2004·23 cites·18 claims
- 1375US7253049B2Method for fabricating dual work function metal gatesTEXAS INSTRUMENTS INC·Filed 2004·Granted Aug 7, 2007·19 cites·30 claims
- 1475US7208409B2Integrated circuit metal silicide methodTEXAS INSTRUMENTS INC·Filed 2005·Granted Apr 24, 2007·6 cites·20 claims
- 1575US6218732B1Copper bond pad processTEXAS INSTRUMENTS INC·Filed 1999·Granted Apr 17, 2001·46 cites·11 claims
- 1673US7148143B2Semiconductor device having a fully silicided gate electrode and method of manufacture thereforTEXAS INSTRUMENTS INC·Filed 2004·Granted Dec 12, 2006·15 cites·18 claims
- 1772US7183187B2Integration scheme for using silicided dual work function metal gatesTEXAS INSTRUMENTS INC·Filed 2004·Granted Feb 27, 2007·16 cites·15 claims
- 1872US6787429B2High-K dielectric materials and processes for manufacturing themMICRON TECHNOLOGY INC·Filed 2002·Granted Sep 7, 2004·9 cites·16 claims
- 1972US6730597B1Pre-ECD wet surface modification to improve wettability and reduced void defectTEXAS INSTRUMENTS INC·Filed 2000·Granted May 4, 2004·13 cites·17 claims
- 2071US7422968B2Method for manufacturing a semiconductor device having silicided regionsTEXAS INSTRUMENTS INC·Filed 2004·Granted Sep 9, 2008·16 cites·20 claims
- 2170US8835263B2Formation of a selective carbon-doped epitaxial cap layer on selective epitaxial SiGeWEIJTMANS JOHAN·Filed 2007·Granted Sep 16, 2014·6 cites·17 claims
- 2269US7338888B2Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the sameTEXAS INSTRUMENTS INC·Filed 2004·Granted Mar 4, 2008·12 cites·16 claims
- 2368US6680249B2Si-rich surface layer capped diffusion barriersTEXAS INSTRUMENTS INC·Filed 2002·Granted Jan 20, 2004·14 cites·10 claims
- 2466US7335595B2Silicide formation using a low temperature anneal processTEXAS INSTRUMENTS INC·Filed 2005·Granted Feb 26, 2008·3 cites·18 claims
- 2565US8546259B2Nickel silicide formation for semiconductor componentsDELOACH JUANITA·Filed 2007·Granted Oct 1, 2013·3 cites·34 claims
- 2665US7585738B2Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related deviceTEXAS INSTRUMENTS INC·Filed 2007·Granted Sep 8, 2009·2 cites·13 claims
- 2764US7943499B2FUSI integration method using SOG as a sacrificial planarization layerTEXAS INSTRUMENTS INC·Filed 2009·Granted May 17, 2011·1 cites·13 claims
- 2864US7655555B2In-situ co-deposition of Si in diffusion barrier material depositions with improved wettability, barrier efficiency, and device reliabilityTEXAS INSTRUMENTS INC·Filed 2001·Granted Feb 2, 2010·9 cites·11 claims
- 2962US6927159B2Methods for providing improved layer adhesion in a semiconductor deviceTEXAS INSTRUMENTS INC·Filed 2003·Granted Aug 9, 2005·8 cites·3 claims
- 3061US6800547B2Integrated circuit dielectric and methodTEXAS INSTRUMENTS INC·Filed 2001·Granted Oct 5, 2004·5 cites·2 claims
- 3161US6784093B1Copper surface passivation during semiconductor manufacturingTEXAS INSTRUMENTS INC·Filed 2003·Granted Aug 31, 2004·9 cites·30 claims
- 3260US7029967B2Silicide method for CMOS integrated circuitsTEXAS INSTRUMENTS INC·Filed 2004·Granted Apr 18, 2006·7 cites·12 claims
- 3359US9048180B2Low stress sacrificial cap layerLU JIONG-PING·Filed 2006·Granted Jun 2, 2015·1 cites·14 claims
- 3459US6120842ATiN+Al films and processesTEXAS INSTRUMENTS INC·Filed 1997·Granted Sep 19, 2000·22 cites·10 claims
- 3558US7732313B2FUSI integration method using SOG as a sacrificial planarization layerTEXAS INSTRUMENTS INC·Filed 2009·Granted Jun 8, 2010·0 cites·2 claims
- 3657US6583053B2Use of a sacrificial layer to facilitate metallization for small featuresTEXAS INSTRUMENTS INC·Filed 2001·Granted Jun 24, 2003·6 cites·16 claims
- 3757US6544886B2Process for isolating an exposed conducting surfaceTEXAS INSTRUMENTS INC·Filed 2000·Granted Apr 8, 2003·6 cites·8 claims
- 3856US6831008B2Nickel silicide—silicon nitride adhesion through surface passivationTEXAS INSTRUMENTS INC·Filed 2002·Granted Dec 14, 2004·5 cites·15 claims
- 3956US6734099B2System for preventing excess silicon consumption in ultra shallow junctionsTEXAS INSTURMENTS INC·Filed 2002·Granted May 11, 2004·7 cites·19 claims
- 4056US6559050B1Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devicesTEXAS INSTRUMENTS INC·Filed 2000·Granted May 6, 2003·7 cites·9 claims
- 4156US6245672B1Method of forming diffusion barriers for copper metallization in integrated cirucitsTEXAS INSTRUMENTS INC·Filed 1998·Granted Jun 12, 2001·20 cites·28 claims
- 4255US7732852B2High-K dielectric materials and processes for manufacturing themMICRON TECHNOLOGY INC·Filed 2006·Granted Jun 8, 2010·0 cites·7 claims
- 4355US7253124B2Process for defect reduction in electrochemical platingTEXAS INSTRUMENTS INC·Filed 2001·Granted Aug 7, 2007·4 cites·9 claims
- 4454US7994073B2Low stress sacrificial cap layerTEXAS INSTRUMENTS INC·Filed 2007·Granted Aug 9, 2011·0 cites·18 claims
- 4554US7101788B2Semiconductor devices and methods of manufacturing such semiconductor devicesTEXAS INSTRUMENTS INC·Filed 2003·Granted Sep 5, 2006·4 cites·14 claims
- 4654US6861695B2High-k dielectric materials and processes for manufacturing themMICRON TECHNOLOGY INC·Filed 2002·Granted Mar 1, 2005·2 cites·7 claims
- 4753US8053296B2Capacitor formed on a recrystallized polysilicon layerTEXAS INSTRUMENTS INC·Filed 2009·Granted Nov 8, 2011·0 cites·10 claims
- 4853US7666729B2Method for improving the thermal stability of silicideTEXAS INSTRUMENTS INC·Filed 2006·Granted Feb 23, 2010·0 cites·13 claims
- 4952US7732312B2FUSI integration method using SOG as a sacrificial planarization layerTEXAS INSTRUMENTS INC·Filed 2006·Granted Jun 8, 2010·0 cites·15 claims
- 5052US6630394B2System for reducing silicon-consumption through selective depositionTEXAS INSTRUMENTS INC·Filed 2002·Granted Oct 7, 2003·5 cites·17 claims
Showing the top 50 of 89 patent records by PatentIndex Score.
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