Inventor · disambiguated record
Kathleen C. Yu
Also filed as: YU KATHLEEN C
11 granted patents·1 pending application·420 citations·filing 1998–2007
92Inventor score
Top patents by PatentIndex Score
12 records- 0193US6037668AIntegrated circuit having a support structureMOTOROLA INC·Filed 1998·Granted Mar 14, 2000·136 cites·19 claims
- 0290US6838332B1Method for forming a semiconductor device having electrical contact from opposite sidesFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jan 4, 2005·45 cites·14 claims
- 0388US6764919B2Method for providing a dummy feature and structure thereofMOTOROLA INC·Filed 2002·Granted Jul 20, 2004·50 cites·11 claims
- 0488US6313024B1Method for forming a semiconductor deviceMOTOROLA INC·Filed 1999·Granted Nov 6, 2001·81 cites·20 claims
- 0584US6921961B2Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion regionFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jul 26, 2005·28 cites·11 claims
- 0681US7030001B2Method for forming a gate electrode having a metalFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Apr 18, 2006·31 cites·38 claims
- 0780US6838354B2Method for forming a passivation layer for air gap formationFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Jan 4, 2005·24 cites·17 claims
- 0878US7122421B2Semiconductor device including a transistor and a capacitor having an aligned transistor and capacitive elementFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Oct 17, 2006·6 cites·8 claims
- 0969US6815820B2Method for forming a semiconductor interconnect with multiple thicknessFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Nov 9, 2004·14 cites·16 claims
- 1057US7904869B2Method of area compaction for integrated circuit layout designFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Mar 8, 2011·2 cites·14 claims
- 1149US7176574B2Semiconductor device having a multiple thickness interconnectFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Feb 13, 2007·3 cites·7 claims
- 1241US2007072334A1Semiconductor fabrication process employing spacer defined viasFREESCALE SEMICONDUCTOR INC·Filed 2005·Application pending·0 cites
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