Inventor · disambiguated record
Ujval J. Kapasi
Also filed as: KAPASI UJVAL · KAPASI UJVAL J
15 granted patents·2 pending applications·197 citations·filing 1998–2024
93Inventor score
Files withOL SECURITY LLC4UNIV LELAND STANFORD JUNIOR3CALOS FUND LTD LIABILITY COMPANY2KAPASI UJVAL J2NVIDIA CORP2
Top patents by PatentIndex Score
17 records- 0196US8786614B2Chaining image-processing functions on a SIMD processorCALOS FUND LTD LIABILITY COMPANY·Filed 2013·Granted Jul 22, 2014·53 cites·20 claims
- 0294US12170765B2Hierarchical packing of syntax elementsOL SECURITY LLC·Filed 2023·Granted Dec 17, 2024·2 cites·27 claims
- 0390US7818539B2System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector valuesUNIV LELAND STANFORD JUNIOR·Filed 2006·Granted Oct 19, 2010·23 cites·3 claims
- 0484US8213509B2Video coding on parallel processing systemsKAPASI UJVAL J·Filed 2007·Granted Jul 3, 2012·6 cites·31 claims
- 0583US10841579B2Hierarchical packing of syntax elementsOL SECURITY LLC·Filed 2017·Granted Nov 17, 2020·2 cites·20 claims
- 0683US7669041B2Instruction-parallel processor with zero-performance-overhead operand copySTREAM PROCESSORS INC·Filed 2007·Granted Feb 23, 2010·19 cites·20 claims
- 0783US2025119537A1Hierarchical packing of syntax elementsOL SECURITY LLC·Filed 2024·Application pending·0 cites
- 0881US11665342B2Hierarchical packing of syntax elementsOL SECURITY LLC·Filed 2020·Granted May 30, 2023·1 cites·27 claims
- 0980US7100026B2System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector valuesUNIV LELAND STANFORD JUNIOR·Filed 2001·Granted Aug 29, 2006·27 cites·14 claims
- 1077US9667962B2Hierarchical packing of syntax elementsOL SECURITY LTD LIABILITY COMPANY·Filed 2014·Granted May 30, 2017·2 cites·20 claims
- 1176US10997492B2Automated methods for conversions to a lower precision data formatNVIDIA CORP·Filed 2017·Granted May 4, 2021·4 cites·28 claims
- 1272US8861611B2Hierarchical packing of syntax elementsKAPASI UJVAL J·Filed 2008·Granted Oct 14, 2014·2 cites·18 claims
- 1369US8412917B2Data exchange and communication between execution units in a parallel processorKHAILANY BRUCEK·Filed 2011·Granted Apr 2, 2013·2 cites·17 claims
- 1467US8024553B2Data exchange and communication between execution units in a parallel processorCALOS FUND LTD LIABILITY COMPANY·Filed 2008·Granted Sep 20, 2011·3 cites·14 claims
- 1566US6269435B1System and method for implementing conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vectorUNIV LELAND STANFORD JUNIOR·Filed 1998·Granted Jul 31, 2001·51 cites·8 claims
- 1657US2021256348A1Automated methods for conversions to a lower precision data formatNVIDIA CORP·Filed 2021·Application pending·0 cites
- 1740US8456480B2Method for chaining image-processing functions on a SIMD processorCURRY DONALD JAMES·Filed 2010·Granted Jun 4, 2013·0 cites·16 claims
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