Inventor

AJANOVIC JASMIN

US88 patents

⚠️ This page may combine multiple inventors who share the name “AJANOVIC JASMIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AJANOVIC JASMIN

INTEL CORP

General input/output architecture, protocol and related methods to implement flow control

Controller configurable for use with multiple memory organizations

Method and apparatus for arbitrating between command streams

General input/output architecture, protocol and related methods to support legacy interrupts

Enhanced general input/output architecture and related methods for establishing virtual channels therein

General input/output architecture, protocol and related methods to manage data integrity

Method and apparatus for initializing a computer interface

Time-distributed ECC scrubbing to correct memory errors

General input/output architecture with PCI express protocol with credit-based flow control

Transmitting peer-to-peer transactions through a coherent interface

Method and apparatus for an improved interface between computer components

Method and apparatus for improving system performance when reordering commands

PCI express enhancements and extensions

Method and apparatus for dynamically deferring transactions

Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer

General input/output architecture, protocol and related methods to implement flow control

General input/output architecture, protocol and related methods to implement flow control

General input/output architecture, protocol and related methods to implement flow control

General input/output architecture, protocol and related methods to implement flow control

Communicating transaction types between agents in a computer system using packet headers including format and type fields

Method for handling completion packets with a non-successful completion status

General input/output architecture, protocol and related methods to provide isochronous channels

Enhanced general input/output architecture and related methods for establishing virtual channels therein

Method and system to improve prefetching operations

Method and apparatus for mode selection in a computer system

Method and apparatus for intializing a hub interface

Method and apparatus for arbitrating ownership of an interface between hub agents

Method and apparatus for throttling high priority memory accesses

Efficient communication of transaction types using separate and orthogonal attribute fields in packet headers transferred between hubs in a computer system

Method and apparatus for selectively receiving write data within a write buffer of a host bridge

PCI express enhancements and extensions

PCI express enhancements and extensions

Peripheral component interconnect (PCI) configuration emulation for hub interface

Configurable page closing method and apparatus for multi-port host bridges

Method and apparatus for communicating routing and attribute information for a transaction between hubs in a computer system

Configurable page closing method and apparatus for multi-port host bridges

Fast address latch with automatic address incrementing

General input/output architecture, protocol and related methods to manage data integrity

Triple-port bus bridge

Computer card insertion detection circuit

Peer-to-peer bus segment bridging

AJANOVIC JASMIN

PCI express enhancements and extensions

General input/output architecture, protocol and related methods to implement flow control

PCI express enhancements and extensions

PCI express enhancements and extensions

PCI express enhancements and extensions including device window caching

PCI express enhancements and extensions

PCI express enhancements and extensions

PCI express enhancements and extensions including transactions having prefetch parameters

PCI express enhancements and extensions