Inventor · disambiguated record
Yiu-Fai Chan
Also filed as: CHAN YIU-FAI
15 granted patents·2,863 citations·filing 1982–2006
96Inventor score
Top patents by PatentIndex Score
15 records- 0199US6539072B1Delay locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 2000·Granted Mar 25, 2003·263 cites·31 claims
- 0299US6125157ADelay-locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 1997·Granted Sep 26, 2000·382 cites·20 claims
- 0398US4713792AProgrammable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuitsALTERA CORP·Filed 1985·Granted Dec 15, 1987·257 cites·19 claims
- 0498US4617479AProgrammable logic array device using EPROM technologyALTERA CORP·Filed 1984·Granted Oct 14, 1986·361 cites·27 claims
- 0597US4774421AProgrammable logic array device using EPROM technologyALTERA CORP·Filed 1986·Granted Sep 27, 1988·194 cites·27 claims
- 0697US4609986AProgrammable logic array device using EPROM technologyALTERA CORP·Filed 1984·Granted Sep 2, 1986·442 cites·18 claims
- 0797US4486670AMonolithic CMOS low power digital level shifterINTERSIL INC·Filed 1982·Granted Dec 4, 1984·105 cites·8 claims
- 0896US5945862ACircuitry for the delay adjustment of a clock signalRAMBUS INC·Filed 1997·Granted Aug 31, 1999·152 cites·16 claims
- 0995US5111423AProgrammable interface for computer system peripheral circuit cardALTERA CORP·Filed 1988·Granted May 5, 1992·243 cites·19 claims
- 1093US6047346ASystem for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output driversRAMBUS INC·Filed 1998·Granted Apr 4, 2000·268 cites·24 claims
- 1191US7039147B2Delay locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 2003·Granted May 2, 2006·34 cites·62 claims
- 1290US7308065B2Delay locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 2006·Granted Dec 11, 2007·15 cites·19 claims
- 1390US4969121AProgrammable integrated circuit logic array device having improved microprocessor connectabilityALTERA CORP·Filed 1987·Granted Nov 6, 1990·55 cites·21 claims
- 1490US4930107AMethod and apparatus for programming and verifying programmable elements in programmable devicesALTERA CORP·Filed 1988·Granted May 29, 1990·51 cites·24 claims
- 1585US5066873AIntegrated circuits with reduced switching noiseALTERA CORP·Filed 1989·Granted Nov 19, 1991·41 cites·25 claims
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