Inventor · disambiguated record
Sorin Iacobovici
Also filed as: IACOBOVICI SORIN
32 granted patents·12 pending applications·836 citations·filing 1994–2017
98Inventor score
Files withSUN MICROSYSTEMS INC20INTEL CORP6HEWLETT PACKARD CO5INST THE DEV OF EMERGING ARCHI2HEWLETT PACKARD DEVELOPMENT CO1
Top patents by PatentIndex Score
44 records- 0195US7487296B1Multi-stride prefetcher with a recurring prefetch tableSUN MICROSYSTEMS INC·Filed 2005·Granted Feb 3, 2009·53 cites·39 claims
- 0294US7555692B1End-to-end residue based protection of an execution pipelineSUN MICROSYSTEMS INC·Filed 2005·Granted Jun 30, 2009·40 cites·17 claims
- 0391US7418582B1Versatile register file design for a multi-threaded processor utilizing different modes and register windowsSUN MICROSYSTEMS INC·Filed 2004·Granted Aug 26, 2008·70 cites·24 claims
- 0489US7996663B2Saving and restoring architectural state for processor coresINTEL CORP·Filed 2007·Granted Aug 9, 2011·26 cites·23 claims
- 0588US7769795B1End-to-end residue-based protection of an execution pipeline that supports floating point operationsORACLE AMERICA INC·Filed 2005·Granted Aug 3, 2010·20 cites·12 claims
- 0686US9110768B2Residue based error detection for integer and floating point execution unitsINTEL CORP·Filed 2012·Granted Aug 18, 2015·9 cites·15 claims
- 0785US8412981B2Core sparing on multi-core platformsMUNOZ ALBERTO J·Filed 2006·Granted Apr 2, 2013·19 cites·34 claims
- 0882US7325101B1Techniques for reducing off-chip cache memory accessesSUN MICROSYSTEMS INC·Filed 2005·Granted Jan 29, 2008·11 cites·30 claims
- 0981US7340590B1Handling register dependencies between instructions specifying different width registersSUN MICROSYSTEMS INC·Filed 2003·Granted Mar 4, 2008·33 cites·30 claims
- 1080US10491381B2In-field system test securityINTEL CORP·Filed 2017·Granted Nov 26, 2019·2 cites·25 claims
- 1180US6704876B1Microprocessor speed control mechanism using power dissipation estimation based on the instruction data pathSUN MICROSYSTEMS INC·Filed 2000·Granted Mar 9, 2004·31 cites·13 claims
- 1279US6185660B1Pending access queue for providing data to a target register during an intermediate pipeline phase after a computer cache missHEWLETT PACKARD CO·Filed 1997·Granted Feb 6, 2001·84 cites·4 claims
- 1378US5652859AMethod and apparatus for handling snoops in multiprocessor caches having internal buffer queuesINST THE DEV OF EMERGING ARCHI·Filed 1995·Granted Jul 29, 1997·84 cites·8 claims
- 1475US7543007B2Residue-based error detection for a shift operationSUN MICROSYSTEMS INC·Filed 2005·Granted Jun 2, 2009·7 cites·19 claims
- 1574US5493723AProcessor with in-system emulation circuitry which uses the same group of terminals to output program counter bitsNAT SEMICONDUCTOR CORP·Filed 1994·Granted Feb 20, 1996·84 cites·10 claims
- 1670US5664148ACache arrangement including coalescing buffer queue for non-cacheable dataINST THE DEV OF EMERGING ARCHI·Filed 1995·Granted Sep 2, 1997·59 cites·8 claims
- 1769US9654143B2Consecutive bit error detection and correctionINTEL CORP·Filed 2014·Granted May 16, 2017·4 cites·15 claims
- 1869US7191316B2Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction streamSUN MICROSYSTEMS INC·Filed 2003·Granted Mar 13, 2007·16 cites·22 claims
- 1966US5995967AForming linked lists using content addressable memoryHEWLETT PACKARD CO·Filed 1996·Granted Nov 30, 1999·41 cites·13 claims
- 2063US7065635B1Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processorSUN MICROSYSTEMS INC·Filed 2003·Granted Jun 20, 2006·10 cites·15 claims
- 2163US6820086B1Forming linked lists using content addressable memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Nov 16, 2004·23 cites·15 claims
- 2262US5860095AConflict cache having cache miscounters for a computer memory systemHEWLETT PACKARD CO·Filed 1996·Granted Jan 12, 1999·40 cites·6 claims
- 2354US7124284B2Method and apparatus for processing a complex instruction for execution and retirementSUN MICROSYSTEMS INC·Filed 2003·Granted Oct 17, 2006·4 cites·19 claims
- 2453US7080237B2Register window flattening logic for dependency checking among instructionsSUN MICROSYSTEMS INC·Filed 2002·Granted Jul 18, 2006·3 cites·5 claims
- 2552US6055610ADistributed memory multiprocessor computer system with directory based cache coherency with ambiguous mapping of cached data to main-memory locationsHEWLETT PACKARD CO·Filed 1997·Granted Apr 25, 2000·23 cites·6 claims
- 2651US7024541B2Register window spill technique for retirement window having entry size less than amount of spill instructionsSUN MICROSYSTEMS INC·Filed 2002·Granted Apr 4, 2006·4 cites·8 claims
- 2748US5696939AApparatus and method using a semaphore buffer for semaphore instructionsHEWLETT PACKARD CO·Filed 1995·Granted Dec 9, 1997·21 cites·9 claims
- 2847US2010257294A1Configurable provisioning of computer system resourcesREGNIER GREG·Filed 2009·Application pending·0 cites
- 2946US10859627B2In-field system testingINTEL CORP·Filed 2017·Granted Dec 8, 2020·0 cites·25 claims
- 3046US7043609B2Method and apparatus for protecting a state associated with a memory structureSUN MICROSYSTEMS INC·Filed 2003·Granted May 9, 2006·2 cites·21 claims
- 3145US2008065835A1Offloading operations for maintaining data coherence across a plurality of nodesSUN MICROSYSTEMS INC·Filed 2006·Application pending·0 cites
- 3243US7219218B2Vector technique for addressing helper instruction groups associated with complex instructionsSUN MICROSYSTEMS INC·Filed 2003·Granted May 15, 2007·0 cites·53 claims
- 3343US2004193844A1Load and/or store queue emptying technique to facilitate atomicity in processor execution of helper setSUN MICROSYSTEMS INC·Filed 2003·Application pending·0 cites
- 3443US2004193845A1Stall technique to facilitate atomicity in processor execution of helper setSUN MICROSYSTEMS INC·Filed 2003·Application pending·0 cites
- 3542US2004153631A1Method to handle instructions that use non-windowed registers in a windowed microprocessor capable of out-of-order executionFiled 2003·Application pending·0 cites
- 3642US2004215941A1Method and system to handle register window fill and spillSUN MICROSYSTEMS INC·Filed 2003·Application pending·0 cites
- 3742US2004162972A1Method for handling control transfer instruction couples in out-of-order, multi-issue, multi-stranded processorFiled 2003·Application pending·0 cites
- 3842US2004199749A1Method and apparatus to limit register file read ports in an out-of-order, multi-stranded processorFiled 2003·Application pending·0 cites
- 3942US2004128488A1Strand switching algorithm to avoid strand starvationFiled 2002·Application pending·0 cites
- 4042US2004128476A1Scheme to simplify instruction buffer logic supporting multiple strandsFiled 2002·Application pending·0 cites
- 4141US2004148497A1Method and apparatus for determining an early reifetch address of a mispredicted conditional branch instruction in an out of order multi-issue processorVAHIDSAFA ALI·Filed 2003·Application pending·0 cites
- 4241US2004044881A1Method and system for early speculative store-load bypassSUN MICROSYSTEMS INC·Filed 2002·Application pending·0 cites
- 4340US7035999B2Register window fill technique for retirement window having entry size less than amount of fill instructionsSUN MICROSYSTEMS INC·Filed 2002·Granted Apr 25, 2006·0 cites·8 claims
- 4440US6453427B2Method and apparatus for handling data errors in a computer systemINTEL CORP·Filed 1998·Granted Sep 17, 2002·13 cites·20 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →