Inventor · disambiguated record
Kwangsoo Han
Also filed as: HAN KWANGSOO
11 granted patents·21 citations·filing 2014–2023
84Inventor score
Top patents by PatentIndex Score
11 records- 0193US10963618B1Multi-dimension clock gate design in clock tree synthesisCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 30, 2021·5 cites·20 claims
- 0288US10643019B1View pruning for routing tree optimizationCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted May 5, 2020·6 cites·20 claims
- 0386US10614261B1Honoring pin insertion delay during clock tree synthesisCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Apr 7, 2020·5 cites·20 claims
- 0477US10713406B2Multi-die IC layout methods with awareness of mix and match die integrationUNIV CALIFORNIA·Filed 2016·Granted Jul 14, 2020·3 cites·16 claims
- 0564US9620844B2Connector joint support module, electronic device including the same, and methods of assembling and disassembling electronic deviceSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted Apr 11, 2017·2 cites·18 claims
- 0657US12487562B2Wearable electronic device including wheelSAMSUNG ELECTRONICS CO LTD·Filed 2023·Granted Dec 2, 2025·0 cites·20 claims
- 0757US12400059B1Logic sharing maximization using non-unique matrix representationCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Aug 26, 2025·0 cites·20 claims
- 0851US12481811B1Circuit design modification based on timing tradeoffCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Nov 25, 2025·0 cites·20 claims
- 0951US12153383B2Electronic device including detachable ornamental memberSAMSUNG ELECTRONICS CO LTD·Filed 2021·Granted Nov 26, 2024·0 cites·18 claims
- 1049US10796049B1Waveform propagation timing modeling for circuit designCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Oct 6, 2020·0 cites·20 claims
- 1146US12422786B2Wearable electronic deviceSAMSUNG ELECTRONICS CO LTD·Filed 2022·Granted Sep 23, 2025·0 cites·19 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →