Inventor

HOWARD GREGORY E

US62 patents

⚠️ This page may combine multiple inventors who share the name “HOWARD GREGORY E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOWARD GREGORY E

TEXAS INSTRUMENTS INC

Advanced CMOS using super steep retrograde wells

Advanced CMOS using super steep retrograde wells

Advanced CMOS using super steep retrograde wells

Advanced CMOS using super steep retrograde wells

Advanced CMOS using super steep retrograde wells

Array-processed stacked semiconductor packages

Programmable neuron MOSFET on SOI

Scribe street width reduction by deep trench and shallow saw cut

RF voltage controlled capacitor on thick-film SOI

Blocking of boron diffusion through the emitter-emitter poly interface in PNP HBTs through use of a SiC layer at the top of the emitter epi layer

On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits

Integrated process for high voltage and high performance silicon-on-insulator bipolar devices

Integrated process for high voltage and high performance silicon-on-insulator bipolar devices

High breakdown voltage transistor and method

P-i-n transit time silicon-on-insulator device

Ball grid array package for high speed devices

Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor device

On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits

Lateral heterojunction bipolar transistor

Semiconductor package having etched foil capacitor integrated into leadframe

IC having voltage regulated integrated Faraday shield

Heat extraction from packaged semiconductor chips, scalable with chip area

Galvanic isolator

Semiconductor package having a grid array of pin-attached balls

Via structure of packages for high frequency semiconductor devices

Carbide emitter mask etch stop

Semiconductor packages for enhanced number of terminals, speed and power performance

Double diffused vertical JFET

Semiconductor circuit with mechanically attached lid

Carbide emitter mask etch stop

Heat extraction from packaged semiconductor chips, scalable with chip area

Bipolar junction transistor with a counterdoped collector region

System and method to improve IC fabrication through selective fusing

Method for constructing a metal oxide semiconductor field effect transistor

System and method for modeling an integrated circuit system

MOSFET having channel in bulk semiconductor and source/drain on insulator, and method of fabrication

Semiconductor packages for enhanced number of terminals, speed and power performance

Bipolar transistor having base over buried insulating and polycrystalline regions

Method of forming integrated circuit contacts

Implant-controlled-channel vertical JFET

Method of forming integrated circuit contacts

Variable thickness single mask etch process

Versatile system for cross-lateral junction field effect transistor

BABCOCK JEFFREY A

Advanced CMOS using super steep retrograde wells

Control of dopant diffusion from buried layers in bipolar integrated circuits

Advanced CMOS using super steep retrograde wells

HOWARD GREGORY E

Apparatus for broadband matching

Differential transmission line pairs using a coupling orthogonalization approach to reduce cross-talk

Structure for high-speed signal integrity in semiconductor package with single-metal-layer substrate

(unassigned)

Blocking of boron diffusion through the emitter-emitter poly interface in PNP HBTs through use of a SiC layer at the top of the emitter epi layer