Inventor · disambiguated record
Donald C. Stark
Also filed as: STARK DONALD · STARK DONALD C · STARK DONALD CHARLES
116 granted patents·8 pending applications·5,929 citations·filing 1993–2017
99Inventor score
Top patents by PatentIndex Score
124 records- 0199US6889304B2Memory device supporting a dynamically configurable core organizationRAMBUS INC·Filed 2002·Granted May 3, 2005·314 cites·14 claims
- 0299US6701446B2Power control system for synchronous memory deviceRAMBUS INC·Filed 2001·Granted Mar 2, 2004·184 cites·40 claims
- 0399US6646953B1Single-clock, strobeless signaling systemRAMBUS INC·Filed 2000·Granted Nov 11, 2003·174 cites·51 claims
- 0499US6643787B1Bus system optimizationRAMBUS INC·Filed 1999·Granted Nov 4, 2003·424 cites·6 claims
- 0599US6539072B1Delay locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 2000·Granted Mar 25, 2003·263 cites·31 claims
- 0699US6496897B2Semiconductor memory device which receives write masking informationRAMBUS INC·Filed 2001·Granted Dec 17, 2002·148 cites·39 claims
- 0799US6125157ADelay-locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 1997·Granted Sep 26, 2000·382 cites·20 claims
- 0898US6950956B2Integrated circuit with timing adjustment mechanism and methodRAMBUS INC·Filed 2003·Granted Sep 27, 2005·169 cites·21 claims
- 0998US6493789B2Memory device which receives write masking and automatic precharge informationRAMBUS INC·Filed 2001·Granted Dec 10, 2002·147 cites·36 claims
- 1098US6401167B1High performance cost optimized memoryRAMBUS INC·Filed 1998·Granted Jun 4, 2002·168 cites·67 claims
- 1198US5748914AProtocol for communication with dynamic memoryRAMBUS INC·Filed 1995·Granted May 5, 1998·227 cites·19 claims
- 1297US7535933B2Calibrated data communication system and methodRAMBUS INC·Filed 2006·Granted May 19, 2009·58 cites·17 claims
- 1397US7287119B2Integrated circuit memory device with delayed write command processingRAMBUS INC·Filed 2007·Granted Oct 23, 2007·40 cites·23 claims
- 1497US7197611B2Integrated circuit memory device having write latency functionRAMBUS INC·Filed 2005·Granted Mar 27, 2007·54 cites·27 claims
- 1597US7042914B2Calibrated data communication system and methodRAMBUS INC·Filed 2003·Granted May 9, 2006·93 cites·17 claims
- 1697US5479370ASemiconductor memory with bypass circuitTOSHIBA KK·Filed 1995·Granted Dec 26, 1995·196 cites·27 claims
- 1796US8059476B2Control component for controlling a delay interval within a memory componentWARE FREDERICK A·Filed 2010·Granted Nov 15, 2011·15 cites·21 claims
- 1896US6990042B2Single-clock, strobeless signaling systemRAMBUS INC·Filed 2005·Granted Jan 24, 2006·33 cites·21 claims
- 1996US6681288B2Memory device with receives write masking informationRAMBUS INC·Filed 2002·Granted Jan 20, 2004·85 cites·39 claims
- 2096US6470405B2Protocol for communication with dynamic memoryRAMBUS INC·Filed 2001·Granted Oct 22, 2002·86 cites·37 claims
- 2196US6266737B1Method and apparatus for providing a memory with write enable informationRAMBUS INC·Filed 2000·Granted Jul 24, 2001·81 cites·25 claims
- 2296US6263448B1Power control system for synchronous memory deviceRAMBUS INC·Filed 1998·Granted Jul 17, 2001·186 cites·35 claims
- 2396US6133773AVariable delay elementRAMBUS INC·Filed 1997·Granted Oct 17, 2000·141 cites·27 claims
- 2496US6075730AHigh performance cost optimized memory with delayed memory writesRAMBUS INC·Filed 1998·Granted Jun 13, 2000·182 cites·6 claims
- 2595US6868474B2High performance cost optimized memoryRAMBUS INC·Filed 2002·Granted Mar 15, 2005·58 cites·6 claims
- 2695US6788594B2Asynchronous, high-bandwidth memory component using calibrated timing elementsRAMBUS INC·Filed 2002·Granted Sep 7, 2004·56 cites·45 claims
- 2795US6591353B1Protocol for communication with dynamic memoryRAMBUS INC·Filed 2000·Granted Jul 8, 2003·88 cites·26 claims
- 2895US6163178AImpedance controlled output driverRAMBUS INC·Filed 1998·Granted Dec 19, 2000·95 cites·29 claims
- 2994US9785589B2Memory controller that calibrates a transmit timing offsetRAMBUS INC·Filed 2016·Granted Oct 10, 2017·7 cites·21 claims
- 3094US7362626B2Asynchronous, high-bandwidth memory component using calibrated timing elementsRAMBUS INC·Filed 2005·Granted Apr 22, 2008·20 cites·20 claims
- 3194US7287109B2Method of controlling a memory device having a memory coreRAMBUS INC·Filed 2004·Granted Oct 23, 2007·57 cites·25 claims
- 3294US7091761B2Impedance controlled output driverRAMBUS INC·Filed 2005·Granted Aug 15, 2006·22 cites·18 claims
- 3394US6378018B1Memory device and system including a low power interfaceINTEL CORP·Filed 1998·Granted Apr 23, 2002·224 cites·32 claims
- 3493US7913104B1Method and apparatus for receive channel data alignment with minimized latency variationXILINX INC·Filed 2007·Granted Mar 22, 2011·36 cites·20 claims
- 3593US6810449B1Protocol for communication with dynamic memoryRAMBUS INC·Filed 2000·Granted Oct 26, 2004·75 cites·21 claims
- 3693USRE37409EMemory and method for sensing sub-groups of memory elementsRAMBUS INC·Filed 2000·Granted Oct 16, 2001·68 cites·65 claims
- 3792US7320082B2Power control system for synchronous memory deviceRAMBUS INC·Filed 2003·Granted Jan 15, 2008·36 cites·35 claims
- 3892US6323706B1Apparatus and method for edge based duty cycle conversionRAMBUS INC·Filed 2000·Granted Nov 27, 2001·43 cites·26 claims
- 3991US9405678B2Flash memory controller with calibrated data communicationRAMBUS INC·Filed 2015·Granted Aug 2, 2016·5 cites·20 claims
- 4091US8305839B2Memory device having multiple power modesTSERN ELY K·Filed 2012·Granted Nov 6, 2012·9 cites·33 claims
- 4191US8170067B2Memory system with calibrated data communicationZERBE JARED LEVAN·Filed 2009·Granted May 1, 2012·16 cites·20 claims
- 4291US7830735B2Asynchronous, high-bandwidth memory component using calibrated timing elementsRAMBUS INC·Filed 2009·Granted Nov 9, 2010·13 cites·27 claims
- 4391US7039147B2Delay locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 2003·Granted May 2, 2006·34 cites·62 claims
- 4491US6035369AMethod and apparatus for providing a memory with write enable informationRAMBUS INC·Filed 1995·Granted Mar 7, 2000·55 cites·52 claims
- 4590US7978802B1Method and apparatus for a mesochronous transmission systemXILINX INC·Filed 2007·Granted Jul 12, 2011·23 cites·20 claims
- 4690US7626880B2Memory device having a read pipeline and a delay locked loopRAMBUS INC·Filed 2005·Granted Dec 1, 2009·13 cites·24 claims
- 4790US7308065B2Delay locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 2006·Granted Dec 11, 2007·15 cites·19 claims
- 4890US6661268B2Charge compensation control circuit and method for use with output driverRAMBUS INC·Filed 2001·Granted Dec 9, 2003·30 cites·6 claims
- 4989US8112608B2Variable-width memoryPEREGO RICHARD E·Filed 2009·Granted Feb 7, 2012·10 cites·31 claims
- 5089US7330953B2Memory system having delayed write timingRAMBUS INC·Filed 2007·Granted Feb 12, 2008·11 cites·28 claims
Showing the top 50 of 124 patent records by PatentIndex Score.
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