Inventor · disambiguated record
An-Min Chiang
Also filed as: CHIANG AN-MIN
14 granted patents·1 pending application·334 citations·filing 1994–2006
93Inventor score
Top patents by PatentIndex Score
15 records- 0186US6514785B1CMOS image sensor n-type pin-diode structureTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Feb 4, 2003·44 cites·32 claims
- 0284US5449639ADisposable metal anti-reflection coating process used together with metal dry/wet etchTAIWAN SEMICONDUCTOR MFG·Filed 1994·Granted Sep 12, 1995·104 cites·24 claims
- 0378US7247909B2Method for forming an integrated circuit with high voltage and low voltage devicesTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jul 24, 2007·7 cites·9 claims
- 0471US6534356B1Method of reducing dark current for an image sensor device via use of a polysilicon padTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Mar 18, 2003·17 cites·24 claims
- 0568US6350127B1Method of manufacturing for CMOS image sensorTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Feb 26, 2002·33 cites·30 claims
- 0660US5915178AMethod for improving the endurance of split gate flash EEPROM devices via the addition of a shallow source side implanted regionTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Jun 22, 1999·26 cites·27 claims
- 0759US5753548AMethod for preventing fluorine outgassing-induced interlevel dielectric delamination on P-channel FETSTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted May 19, 1998·21 cites·20 claims
- 0856US6306678B1Process for fabricating a high quality CMOS image sensorTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Oct 23, 2001·21 cites·17 claims
- 0953US5707896AMethod for preventing delamination of interlevel dielectric layer over FET P+ doped polysilicon gate electrodes on semiconductor integrated circuitsTAIWAN SEMICONDUCTOR MANUACTUR·Filed 1996·Granted Jan 13, 1998·17 cites·18 claims
- 1051US5700739AMethod of multi-step reactive ion etch for patterning adjoining semiconductor metallization layersTAIWAN SEMICONDUCTOR MFG·Filed 1995·Granted Dec 23, 1997·14 cites·16 claims
- 1150US5811343AOxidation method for removing fluorine gas inside polysilicon during semiconductor manufacturing to prevent delamination of subsequent layer induced by fluorine outgassing dielectricTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted Sep 22, 1998·14 cites·3 claims
- 1242US7911022B2Isolation structure in field deviceTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Mar 22, 2011·0 cites·14 claims
- 1342US5652172AMethod for controlling the etch profile of an aperture formed through a multi-layer insulator layerTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted Jul 29, 1997·14 cites·22 claims
- 1437US2007108517A1LDMOS with independently biased sourceTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 1530US6159660AOpposite focus control to avoid keyholes inside a passivation layerTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Dec 12, 2000·2 cites·12 claims
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