Inventor · disambiguated record
Taarinya Polepeddi
Also filed as: POLEPEDDI TAARINYA
9 granted patents·186 citations·filing 2011–2019
90Inventor score
Top patents by PatentIndex Score
9 records- 0197US10241943B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2017·Granted Mar 26, 2019·19 cites·17 claims
- 0297US9619408B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2016·Granted Apr 11, 2017·30 cites·9 claims
- 0396US10282323B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2018·Granted May 7, 2019·14 cites·4 claims
- 0496US9342453B2Memory channel that supports near memory and far memory accessNALE BILL·Filed 2011·Granted May 17, 2016·80 cites·16 claims
- 0594US10282322B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2017·Granted May 7, 2019·14 cites·20 claims
- 0694US9600416B2Apparatus and method for implementing a multi-level memory hierarchyRAMANUJAN RAJ K·Filed 2011·Granted Mar 21, 2017·23 cites·31 claims
- 0786US10691626B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2019·Granted Jun 23, 2020·2 cites·14 claims
- 0882US10719443B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2019·Granted Jul 21, 2020·2 cites·19 claims
- 0980US10241912B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2017·Granted Mar 26, 2019·2 cites·32 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →