Inventor · disambiguated record
Hoichi Cheong
Also filed as: CHEONG HOICHI
36 granted patents·1,040 citations·filing 1994–2012
98Inventor score
Top patents by PatentIndex Score
36 records- 0185US8930678B2Instruction and logic to length decode X86 instructionsMADDURI VENKATESWARA R·Filed 2012·Granted Jan 6, 2015·11 cites·24 claims
- 0284US6553480B1System and method for managing the execution of instruction groups having multiple executable instructionsIBM·Filed 1999·Granted Apr 22, 2003·113 cites·27 claims
- 0383US7266648B2Cache lock mechanism with speculative allocationINTEL CORP·Filed 2005·Granted Sep 4, 2007·14 cites·7 claims
- 0482US5961636ACheckpoint table for selective instruction flushing in a speculative execution unitIBM·Filed 1997·Granted Oct 5, 1999·99 cites·13 claims
- 0582US5584013AHierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cacheIBM·Filed 1994·Granted Dec 10, 1996·88 cites·17 claims
- 0674US6986010B2Cache lock mechanism with speculative allocationINTEL CORP·Filed 2002·Granted Jan 10, 2006·19 cites·14 claims
- 0773US9710277B2Processor power management based on class and content of instructionsMADDURI VENKATESWARA R·Filed 2010·Granted Jul 18, 2017·4 cites·15 claims
- 0872US5887161AIssuing instructions in a processor supporting out-of-order executionIBM·Filed 1997·Granted Mar 23, 1999·62 cites·20 claims
- 0971US5870582AMethod and apparatus for completion of non-interruptible instructions before the instruction is dispatchedIBM·Filed 1997·Granted Feb 9, 1999·60 cites·17 claims
- 1066US6073211AMethod and system for memory updates within a multiprocessor data processing systemIBM·Filed 1997·Granted Jun 6, 2000·51 cites·20 claims
- 1165US6308260B1Mechanism for self-initiated instruction issuing and method thereforIBM·Filed 1998·Granted Oct 23, 2001·41 cites·12 claims
- 1265US5974524AMethod and apparatus for reducing the number of rename registers in a processor supporting out-of-order executionIBM·Filed 1997·Granted Oct 26, 1999·46 cites·22 claims
- 1365US5913048ADispatching instructions in a processor supporting out-of-order executionIBM·Filed 1997·Granted Jun 15, 1999·45 cites·16 claims
- 1462US6098167AApparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order executionIBM·Filed 1997·Granted Aug 1, 2000·40 cites·16 claims
- 1559US5996085AConcurrent execution of machine context synchronization operations and non-interruptible instructionsIBM·Filed 1997·Granted Nov 30, 1999·34 cites·24 claims
- 1659US5694573AShared L2 support for inclusion property in split L1 data and instruction cachesIBM·Filed 1996·Granted Dec 2, 1997·37 cites·2 claims
- 1755US7783871B2Method to remove stale branch predictions for an instruction prior to execution within a microprocessorINTEL CORP·Filed 2003·Granted Aug 24, 2010·4 cites·13 claims
- 1854US6324640B1System and method for dispatching groups of instructions using pipelined register renamingIBM·Filed 1998·Granted Nov 27, 2001·27 cites·14 claims
- 1954US6070235AData processing system and method for capturing history buffer dataIBM·Filed 1997·Granted May 30, 2000·28 cites·23 claims
- 2052US6061777AApparatus and method for reducing the number of rename registers required in the operation of a processorIBM·Filed 1997·Granted May 9, 2000·25 cites·28 claims
- 2152US5533189ASystem and method for error correction code generationIBM·Filed 1994·Granted Jul 2, 1996·24 cites·7 claims
- 2251US7080241B2Mechanism for self-initiated instruction issuing and method thereforIBM·Filed 2001·Granted Jul 18, 2006·1 cites·4 claims
- 2350US5870612AMethod and apparatus for condensed history bufferIBM·Filed 1996·Granted Feb 9, 1999·22 cites·12 claims
- 2449US6898696B1Method and system for efficiently restoring a processor's execution state following an interrupt caused by an interruptible instructionIBM·Filed 1999·Granted May 24, 2005·20 cites·13 claims
- 2549US5860014AMethod and apparatus for improved recovery of processor state using history bufferIBM·Filed 1996·Granted Jan 12, 1999·21 cites·14 claims
- 2647US5897651AInformation handling system including a direct access set associative cache and method for accessing sameIBM·Filed 1995·Granted Apr 27, 1999·21 cites·2 claims
- 2747US5805906AMethod and apparatus for writing information to registers in a data processing system using a number of registers for processing instructionsIBM·Filed 1996·Granted Sep 8, 1998·20 cites·12 claims
- 2844US5875326AData processing system and method for completing out-of-order instructionsIBM·Filed 1997·Granted Feb 23, 1999·16 cites·29 claims
- 2942US5692151AHigh performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory addressIBM·Filed 1994·Granted Nov 25, 1997·13 cites·2 claims
- 3041US6473850B1System and method for handling instructions occurring after an ISYNC instructionIBM·Filed 1999·Granted Oct 29, 2002·15 cites·18 claims
- 3134US5774712AInstruction dispatch unit and method for mapping a sending order of operations to a receiving orderIBM·Filed 1996·Granted Jun 30, 1998·5 cites·36 claims
- 3233US6535973B1Method and system for speculatively issuing instructionsIBM·Filed 1999·Granted Mar 18, 2003·5 cites·10 claims
- 3333US5983341AData processing system and method for extending the time for execution of an instructionIBM·Filed 1997·Granted Nov 9, 1999·4 cites·27 claims
- 3432US5754885AApparatus and method for selecting entries from an arrayIBM·Filed 1996·Granted May 19, 1998·5 cites·17 claims
- 3530US6604173B1System for controlling access to external cache memories of differing sizeIBM·Filed 1995·Granted Aug 5, 2003·0 cites·10 claims
- 3630US5822752AMethod and apparatus for fast parallel determination of queue entriesIBM·Filed 1996·Granted Oct 13, 1998·0 cites·10 claims
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