Inventor · disambiguated record
Karthik Thambidurai
Also filed as: THAMBIDURAI KARTHIK
11 granted patents·75 citations·filing 2011–2015
88Inventor score
Top patents by PatentIndex Score
11 records- 0195US9324687B1Wafer-level passive device integrationMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted Apr 26, 2016·26 cites·20 claims
- 0288US9721912B2Wafer-level chip-scale package device having bump assemblies configured to furnish shock absorber functionalityMAXIM INTEGRATED PRODUCTS·Filed 2014·Granted Aug 1, 2017·10 cites·12 claims
- 0386US9190391B2Three-dimensional chip-to-wafer integrationKELKAR AMIT SUBHASH·Filed 2011·Granted Nov 17, 2015·13 cites·8 claims
- 0485US9040408B1Techniques for wafer-level processing of QFN packagesMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted May 26, 2015·12 cites·22 claims
- 0582US10804233B1Wafer-level chip-scale package device having bump assemblies configured to maintain standoff heightKHANDEKAR VIREN·Filed 2011·Granted Oct 13, 2020·10 cites·12 claims
- 0668US8860222B2Techniques for wafer-level processing of QFN packagesMAXIM INTEGRATED PRODUCTS·Filed 2012·Granted Oct 14, 2014·2 cites·11 claims
- 0765US9806047B2Wafer level device and method with cantilever pillar structureMAXIM INTEGRATED PRODUCTS·Filed 2014·Granted Oct 31, 2017·1 cites·17 claims
- 0860US10304758B1Wafer level package device formed using a wafer level lead frame on a carrier wafer having a similar coefficient of thermal expansion as an active waferMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted May 28, 2019·1 cites·5 claims
- 0954US9472451B2Technique for wafer-level processing of QFN packagesMAXIM INTEGRATED PRODUCTS·Filed 2014·Granted Oct 18, 2016·0 cites·7 claims
- 1046US10032749B2Three-dimensional chip-to-wafer integrationMAXIM INTEGRATED PRODUCTS·Filed 2015·Granted Jul 24, 2018·0 cites·11 claims
- 1142US9425064B2Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packagesMAXIM INTEGRATED PRODUCTS·Filed 2012·Granted Aug 23, 2016·0 cites·15 claims
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