Inventor · disambiguated record
Amir H. Mottaez
Also filed as: MOTTAEZ AMIR H
26 granted patents·44 citations·filing 2010–2015
94Inventor score
Top patents by PatentIndex Score
26 records- 0177US8826218B2Accurate approximation of the objective function for solving the gate-sizing problem using a numerical solverSYNOPSYS INC·Filed 2013·Granted Sep 2, 2014·4 cites·15 claims
- 0276US8799843B1Identifying candidate nets for buffering using numerical methodsSYNOPSYS INC·Filed 2013·Granted Aug 5, 2014·4 cites·15 claims
- 0376US8707242B2Optimizing a circuit design for delay using load-and-slew-independent numerical delay modelsMOTTAEZ AMIR H·Filed 2012·Granted Apr 22, 2014·4 cites·20 claims
- 0475US9064073B2Hyper-concurrent optimization over multi-corner multi-mode scenariosMOTTAEZ AMIR H·Filed 2010·Granted Jun 23, 2015·4 cites·26 claims
- 0574US9454626B2Solving an optimization problem using a constraints solverSYNOPSYS INC·Filed 2013·Granted Sep 27, 2016·3 cites·18 claims
- 0673US8589846B2Modeling transition effects for circuit optimizationSYNOPSYS INC·Filed 2012·Granted Nov 19, 2013·2 cites·18 claims
- 0773US8413099B2Performing scenario reductionMOTTAEZ AMIR H·Filed 2010·Granted Apr 2, 2013·6 cites·18 claims
- 0871US9280625B2Incremental slack margin propagationSYNOPSYS INC·Filed 2015·Granted Mar 8, 2016·1 cites·9 claims
- 0970US8966430B1Robust numerical optimization for optimizing delay, area, and leakage powerSYNOPSYS INC·Filed 2013·Granted Feb 24, 2015·2 cites·15 claims
- 1069US8826217B2Modeling gate size range by using a penalty function in a numerical gate sizing frameworkSYNOPSYS INC·Filed 2013·Granted Sep 2, 2014·2 cites·12 claims
- 1168US8949764B2Excluding library cells for delay optimization in numerical synthesisIYER MAHESH A·Filed 2012·Granted Feb 3, 2015·2 cites·18 claims
- 1267US8707241B2Performing scenario reduction using a dominance relation on a set of cornersMOTTAEZ AMIR H·Filed 2010·Granted Apr 22, 2014·2 cites·27 claims
- 1367US8621405B2Incremental elmore delay calculationIYER MAHESH A·Filed 2012·Granted Dec 31, 2013·2 cites·20 claims
- 1466US8418116B2Zone-based optimization framework for performing timing and design rule optimizationWALKER ROBERT·Filed 2010·Granted Apr 9, 2013·2 cites·20 claims
- 1564US8990750B2Numerical area recoverySYNOPSYS INC·Filed 2013·Granted Mar 24, 2015·1 cites·20 claims
- 1660US9430442B2Solving a gate-sizing optimization problem using a constraints solverSYNOPSYS INC·Filed 2013·Granted Aug 30, 2016·2 cites·15 claims
- 1760US9047426B2Performing scenario reduction in a circuit design flowMOTTAEZ AMIR H·Filed 2010·Granted Jun 2, 2015·1 cites·16 claims
- 1856US8977999B2Numerical delay model for a technology library cell typeSYNOPSYS INC·Filed 2014·Granted Mar 10, 2015·0 cites·15 claims
- 1955US9171122B2Efficient timing calculations in numerical sequential cell sizing and incremental slack margin propagationSYNOPSYS INC·Filed 2012·Granted Oct 27, 2015·0 cites·15 claims
- 2055US8683408B2Sequential sizing in physical synthesisSYNOPSYS INC·Filed 2012·Granted Mar 25, 2014·0 cites·21 claims
- 2152US8762905B2Numerical delay model for a technology library cellIYER MAHESH A·Filed 2012·Granted Jun 24, 2014·0 cites·15 claims
- 2249US10394993B2Discretizing gate sizes during numerical synthesisSYNOPSYS INC·Filed 2013·Granted Aug 27, 2019·0 cites·18 claims
- 2346US9519740B2Determining optimal gate sizes by using a numerical solverIYER MAHESH A·Filed 2012·Granted Dec 13, 2016·0 cites·15 claims
- 2445US8239800B2Method and apparatus for determining a robustness metric for a circuit designIYER MAHESH A·Filed 2010·Granted Aug 7, 2012·0 cites·25 claims
- 2544US8843871B2Estimating optimal gate sizes by using numerical delay modelsMOTTAEZ AMIR H·Filed 2012·Granted Sep 23, 2014·0 cites·18 claims
- 2637US9384309B2Global timing modeling within a local contextIYER MAHESH A·Filed 2010·Granted Jul 5, 2016·0 cites·20 claims
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