Inventor · disambiguated record
Chiao Kai Hwang
Also filed as: HWANG CHIAO K · HWANG CHIAO KAI
24 granted patents·945 citations·filing 2001–2019
96Inventor score
Top patents by PatentIndex Score
24 records- 0198US7346644B1Devices and methods with programmable logic and digital signal processing regionsALTERA CORP·Filed 2006·Granted Mar 18, 2008·101 cites·4 claims
- 0298US6556044B2Programmable logic device including multipliers and configurations thereof to reduce resource utilizationALTERA CORP·Filed 2001·Granted Apr 29, 2003·233 cites·72 claims
- 0398US6538470B1Devices and methods with programmable logic and digital signal processing regionsALTERA CORP·Filed 2001·Granted Mar 25, 2003·318 cites·56 claims
- 0494US10871796B1Global clock and a leaf clock dividerXILINX INC·Filed 2019·Granted Dec 22, 2020·12 cites·20 claims
- 0592US6771094B1Devices and methods with programmable logic and digital signal processing regionsALTERA CORP·Filed 2003·Granted Aug 3, 2004·67 cites·20 claims
- 0691US7216139B2Programmable logic device including multipliers and configurations thereof to reduce resource utilizationALTERA CORP·Filed 2005·Granted May 8, 2007·15 cites·18 claims
- 0790US6693455B2Programmable logic device including multipliers and configurations thereof to reduce resource utilizationALTERA CORPORATIONS·Filed 2003·Granted Feb 17, 2004·39 cites·10 claims
- 0890US6661253B1Passgate structures for use in low-voltage applicationsALTERA CORP·Filed 2001·Granted Dec 9, 2003·29 cites·20 claims
- 0986US7119576B1Devices and methods with programmable logic and digital signal processing regionsALTERA CORP·Filed 2004·Granted Oct 10, 2006·46 cites·35 claims
- 1083US7698358B1Programmable logic device with specialized functional blockALTERA CORP·Filed 2003·Granted Apr 13, 2010·33 cites·34 claims
- 1181US7142010B2Programmable logic device including multipliers and configurations thereof to reduce resource utilizationALTERA CORP·Filed 2003·Granted Nov 28, 2006·21 cites·82 claims
- 1278US9639640B1Generation of delay values for a simulation model of circuit elements in a clock networkXILINX INC·Filed 2015·Granted May 2, 2017·3 cites·20 claims
- 1370US10289784B1Determination of clock path delays and implementation of a circuit designXILINX INC·Filed 2017·Granted May 14, 2019·1 cites·16 claims
- 1468US7800405B2Passgate structures for use in low-voltage applicationsALTERA CORP·Filed 2009·Granted Sep 21, 2010·3 cites·12 claims
- 1561US7557608B2Passgate structures for use in low-voltage applicationsALTERA CORP·Filed 2006·Granted Jul 7, 2009·2 cites·8 claims
- 1659US6566906B1Specialized programmable logic region with low-power modeALTERA CORP·Filed 2001·Granted May 20, 2003·5 cites·44 claims
- 1758US6958624B1Data latch with low-power bypass modeALTERA CORP·Filed 2003·Granted Oct 25, 2005·6 cites·22 claims
- 1854US6586966B1Data latch with low-power bypass modeALTERA CORP·Filed 2001·Granted Jul 1, 2003·5 cites·53 claims
- 1951US7119574B1Passage structures for use in low-voltage applicationsALTERA CORP·Filed 2003·Granted Oct 10, 2006·3 cites·15 claims
- 2050US7660841B2Flexible accumulator in digital signal processing circuitryALTERA CORP·Filed 2004·Granted Feb 9, 2010·1 cites·10 claims
- 2148US8364738B1Programmable logic device with specialized functional blockALTERA CORP·Filed 2010·Granted Jan 29, 2013·0 cites·10 claims
- 2244US9170775B2Flexible accumulator in digital signal processing circuitryZHENG LEON·Filed 2010·Granted Oct 27, 2015·0 cites·15 claims
- 2343US6937062B1Specialized programmable logic region with low-power modeALTERA CORP·Filed 2004·Granted Aug 30, 2005·2 cites·18 claims
- 2436US6714042B1Specialized programmable logic region with low-power modeALTERA CORP·Filed 2003·Granted Mar 30, 2004·0 cites·40 claims
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