Inventor · disambiguated record
Jason M. Agron
Also filed as: AGRON JASON · AGRON JASON M · AGRON JASON MICHAEL
17 granted patents·14 pending applications·14 citations·filing 2013–2023
87Inventor score
Technology areasG06F
Top patents by PatentIndex Score
31 records- 0181US9880842B2Using control flow data structures to direct and track instruction executionINTEL CORP·Filed 2013·Granted Jan 30, 2018·7 cites·23 claims
- 0274US11372775B2Management of the untranslated to translated code steering logic in a dynamic binary translation based processorINTEL CORP·Filed 2020·Granted Jun 28, 2022·1 cites·18 claims
- 0371US11061807B2Trace management during aborted speculative operationsINTEL CORP·Filed 2018·Granted Jul 13, 2021·1 cites·17 claims
- 0470US10114643B2Techniques for detecting return-oriented programmingINTEL CORP·Filed 2013·Granted Oct 30, 2018·3 cites·27 claims
- 0566US9817642B2Apparatus and method for efficient call/return emulation using a dual return stack bufferINTEL CORP·Filed 2015·Granted Nov 14, 2017·1 cites·20 claims
- 0664US9823938B2Providing deterministic, reproducible, and random sampling in a processorINTEL CORP·Filed 2015·Granted Nov 21, 2017·1 cites·17 claims
- 0756US10545735B2Apparatus and method for efficient call/return emulation using a dual return stack bufferINTEL CORP·Filed 2017·Granted Jan 28, 2020·0 cites·22 claims
- 0854US2025028532A1Direct, unconditional jumpINTEL CORP·Filed 2023·Application pending·0 cites
- 0951US12131159B2ISA opcode parameterization and opcode space layout randomizationINTEL CORP·Filed 2020·Granted Oct 29, 2024·0 cites·14 claims
- 1050US2019163642A1Management of the untranslated to translated code steering logic in a dynamic binary translation based processorINTEL CORP·Filed 2017·Application pending·0 cites
- 1150US2024220261A1Instructions and support for conditional load and storeAGRON JASON·Filed 2022·Application pending·0 cites
- 1250US2024220262A1Instructions and support for conditional comparison and testAGRON JASON·Filed 2022·Application pending·0 cites
- 1350US2024220257A1Instructions and support for stack push and popAGRON JASON·Filed 2022·Application pending·0 cites
- 1449US2024220260A1Prefix extensions for extended general purpose registers with optimization features for non-destructive destinations and flags suppressionAGRON JASON·Filed 2022·Application pending·0 cites
- 1547US11048516B2Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit arrayCAPRIOLI PAUL·Filed 2015·Granted Jun 29, 2021·0 cites·14 claims
- 1646US10191745B2Optimized call-return and binary translationINTEL CORP·Filed 2017·Granted Jan 29, 2019·0 cites·25 claims
- 1746US9110723B2Multi-core binary translation task processingINTEL CORP·Filed 2013·Granted Aug 18, 2015·0 cites·23 claims
- 1846US2024111539A1Device, method and system to determine a mode of processor operation based on page table metadataINTEL CORP·Filed 2022·Application pending·0 cites
- 1946US2023418612A1Automatic fusion of arithmetic in-flight instructionsINTEL CORP·Filed 2022·Application pending·0 cites
- 2045US9996356B2Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processorINTEL CORP·Filed 2015·Granted Jun 12, 2018·0 cites·14 claims
- 2144US10296343B2Hybrid atomicity support for a binary translation based microprocessorINTEL CORP·Filed 2017·Granted May 21, 2019·0 cites·19 claims
- 2244US9990233B2Binary translation for multi-processor and multi-core platformsINTEL CORP·Filed 2013·Granted Jun 5, 2018·0 cites·34 claims
- 2344US2023315501A1Performance Monitoring Emulation in Translated Branch Instructions in a Binary Translation-Based ProcessorINTEL CORP·Filed 2022·Application pending·0 cites
- 2443US10387159B2Apparatus and method for architectural performance monitoring in binary translation systemsINTEL CORP·Filed 2015·Granted Aug 20, 2019·0 cites·16 claims
- 2543US10228956B2Supporting binary translation alias detection in an out-of-order processorINTEL CORP·Filed 2016·Granted Mar 12, 2019·0 cites·20 claims
- 2641US2020310798A1Technology For Providing Memory Atomicity With Low OverheadSHEVGOOR MANJUNATH·Filed 2019·Application pending·0 cites
- 2740US10635465B2Apparatuses and methods to prevent execution of a modified instructionINTEL CORP·Filed 2015·Granted Apr 28, 2020·0 cites·16 claims
- 2840US2020210193A1Hardware profiler to track instruction sequence information including a blacklisting mechanism and a whitelisting mechanismINTEL CORP·Filed 2018·Application pending·0 cites
- 2939US2019179766A1Translation table entry prefetching in dynamic binary translation based processorINTEL CORP·Filed 2017·Application pending·0 cites
- 3036US2017286110A1Auxiliary Cache for Reducing Instruction Fetch and Decode Bandwidth RequirementsINTEL CORP·Filed 2016·Application pending·0 cites
- 3136US2017192788A1Binary translation support using processor instruction prefixesINTEL CORP·Filed 2016·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →