Inventor · disambiguated record
Steven E. Washburn
Also filed as: WASHBURN STEVEN E · WASHBURN STEVEN EUGENE
8 granted patents·1 pending application·24 citations·filing 2000–2019
81Inventor score
Files withIBM9
Top patents by PatentIndex Score
9 records- 0177US10565336B2Pessimism reduction in cross-talk noise determination used in integrated circuit designIBM·Filed 2018·Granted Feb 18, 2020·3 cites·12 claims
- 0276US11017137B2Efficient projection based adjustment evaluation in static timing analysis of integrated circuitsIBM·Filed 2019·Granted May 25, 2021·2 cites·15 claims
- 0375US10248753B2Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor valuesIBM·Filed 2016·Granted Apr 2, 2019·2 cites·20 claims
- 0464US10254784B1Using required arrival time constraints for coupled noise analysis and noise aware timing analysis of out-of-context (OOC) hierarchical entitiesIBM·Filed 2018·Granted Apr 9, 2019·1 cites·20 claims
- 0562US6571374B1Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chipsIBM·Filed 2000·Granted May 27, 2003·11 cites·20 claims
- 0655US10552570B2Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor valuesIBM·Filed 2018·Granted Feb 4, 2020·0 cites·20 claims
- 0754US6848089B2Method and apparatus for detecting devices that can latchupIBM·Filed 2002·Granted Jan 25, 2005·5 cites·18 claims
- 0845US10169514B2Approximation of resistor-capacitor circuit extraction for thread-safe design changesIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 0936US2017161425A1Compact modeling analysis of circuit layout shape sectionsIBM·Filed 2015·Application pending·0 cites
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