Inventor · disambiguated record
Andres Teene
Also filed as: TEENE ANDRES · TEENE ANDRES R · TEENE ANDRES ROBERT
9 granted patents·242 citations·filing 1994–2005
89Inventor score
Top patents by PatentIndex Score
9 records- 0180US6272668B1Method for cell swapping to improve pre-layout to post-layout timingHYUNDAI ELECTRONICS AMERICA·Filed 1999·Granted Aug 7, 2001·105 cites·23 claims
- 0274US6854103B2Apparatus and method for visualizing and analyzing resistance networksLSI LOGIC CORP·Filed 2002·Granted Feb 8, 2005·21 cites·25 claims
- 0373US5528447A5-volt tolerant bi-directional i/o pad for 3-volt-optimized integrated circuitsAT & T GLOBAL INF SOLUTION·Filed 1994·Granted Jun 18, 1996·39 cites·8 claims
- 0470US7299431B2Method for tracing paths within a circuitLSI CORP·Filed 2005·Granted Nov 20, 2007·5 cites·21 claims
- 0570US5726997AApparatus and method for testing of integrated circuitsAT & T GLOBAL INF SOLUTION·Filed 1995·Granted Mar 10, 1998·34 cites·33 claims
- 0659US7003753B2Method of generating a physical netlist for a hierarchical integrated circuit designLSI LOGIC CORP·Filed 2003·Granted Feb 21, 2006·7 cites·10 claims
- 0752US6539509B1Clock skew insensitive scan chain reorderingLSI LOGIC CORP·Filed 1996·Granted Mar 25, 2003·16 cites·12 claims
- 0842US5903577AMethod and apparatus for analyzing digital circuitsLSI LOGIC CORP·Filed 1997·Granted May 11, 1999·15 cites·20 claims
- 0932US7570539B2Method for identifying memory bit cells and connectionsLSI CORP·Filed 2005·Granted Aug 4, 2009·0 cites·27 claims
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