Inventor · disambiguated record
Paul B. Ricci
Also filed as: RICCI PAUL · RICCI PAUL B · RICCI PAUL BERNARD
21 granted patents·1 pending application·470 citations·filing 1992–2014
96Inventor score
Top patents by PatentIndex Score
22 records- 0186US7543214B2Method and system for performing CRCMARVELL INT LTD·Filed 2005·Granted Jun 2, 2009·18 cites·20 claims
- 0285US7836379B1Method for computing buffer ECCMARVELL INT LTD·Filed 2006·Granted Nov 16, 2010·24 cites·39 claims
- 0383US7559009B1System and method for performing parity checks in disk storage systemsMARVELL INT LTD·Filed 2006·Granted Jul 7, 2009·10 cites·20 claims
- 0482US7111228B1System and method for performing parity checks in disk storage systemMARVELL INT LTD·Filed 2003·Granted Sep 19, 2006·28 cites·7 claims
- 0580US5511224AConfigurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memoriesUNISYS CORP·Filed 1995·Granted Apr 23, 1996·101 cites·19 claims
- 0679US7813067B1Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk driveMARVELL INT LTD·Filed 2008·Granted Oct 12, 2010·2 cites·12 claims
- 0778US7080188B2Method and system for embedded disk controllersMARVELL INT LTD·Filed 2003·Granted Jul 18, 2006·17 cites·18 claims
- 0877US8270107B1Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk driveHUDIONO LIM·Filed 2011·Granted Sep 18, 2012·3 cites·16 claims
- 0972US5553263ACache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memoryUNISYS CORP·Filed 1993·Granted Sep 3, 1996·60 cites·15 claims
- 1069US8031422B1Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk driveMARVELL INT LTD·Filed 2010·Granted Oct 4, 2011·1 cites·19 claims
- 1167US8638512B1Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk driveHUDIONO LIM·Filed 2012·Granted Jan 28, 2014·1 cites·17 claims
- 1262US5404462ADual bus interface transfer system for central processing moduleUNISYS CORP·Filed 1992·Granted Apr 4, 1995·40 cites·14 claims
- 1360US9001443B1Method and system for testing a controller of a hard disk driveMARVELL INT LTD·Filed 2014·Granted Apr 7, 2015·0 cites·11 claims
- 1455US5509127ATransmission logic apparatus for dual bus networkUNISYS CORP·Filed 1992·Granted Apr 16, 1996·27 cites·16 claims
- 1555US5293621AVarying wait interval retry apparatus and method for preventing bus lockoutUNISYS CORP·Filed 1993·Granted Mar 8, 1994·28 cites·25 claims
- 1653US5809533ADual bus system with multiple processors having data coherency maintenanceUNISYS CORP·Filed 1997·Granted Sep 15, 1998·29 cites·7 claims
- 1751US5444860ATranslator system for message transfers between digital units operating on different message protocols and different clock ratesUNISYS CORP·Filed 1992·Granted Aug 22, 1995·24 cites·3 claims
- 1850US2006230214A1Method and system for embedded disk controllersMARVELL INT LTD·Filed 2006·Application pending·0 cites
- 1947US5495585AProgrammable timing logic system for dual bus interfaceUNISYS CORP·Filed 1992·Granted Feb 27, 1996·19 cites·13 claims
- 2046US5442754AReceiving control logic system for dual bus networkUNISYS CORP·Filed 1992·Granted Aug 15, 1995·18 cites·16 claims
- 2140US5293496AInhibit write apparatus and method for preventing bus lockoutUNISYS CORP·Filed 1993·Granted Mar 8, 1994·12 cites·12 claims
- 2235US5553259AApparatus and method for synchronizing the simultaneous loading of cache program word addresses in dual slice registersUNISYS CORP·Filed 1995·Granted Sep 3, 1996·8 cites·5 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →