Inventor · disambiguated record
Andrew B. Kahng
Also filed as: KAHNG ANDREW · KAHNG ANDREW B
35 granted patents·1 pending application·1,260 citations·filing 1997–2016
98Inventor score
Top patents by PatentIndex Score
36 records- 0199US8185865B2Methods for gate-length biasing using annotation dataGUPTA PUNEET·Filed 2010·Granted May 22, 2012·114 cites·24 claims
- 0298US7873929B2Method, apparatus and system for designing an integrated circuit including generating at least one auxiliary pattern for cell-based optical proximity correctionUNIV CALIFORNIA·Filed 2007·Granted Jan 18, 2011·157 cites·51 claims
- 0398US7640522B2Method and system for placing layout objects in a standard-cell layoutTELA INNOVATIONS INC·Filed 2006·Granted Dec 29, 2009·110 cites·42 claims
- 0498US7149999B2Method for correcting a mask design layoutUNIV MICHIGAN·Filed 2004·Granted Dec 12, 2006·233 cites·37 claims
- 0597US7441211B1Gate-length biasing for digital circuit optimizationBLAZE DFM INC·Filed 2005·Granted Oct 21, 2008·280 cites·36 claims
- 0696US7743349B2Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuitTELA INNOVATIONS INC·Filed 2005·Granted Jun 22, 2010·28 cites·13 claims
- 0795US8751974B2Layout decomposition for double patterning lithographyUNIV CALIFORNIA·Filed 2013·Granted Jun 10, 2014·22 cites·11 claims
- 0895US8402396B2Layout decomposition for double patterning lithographyKAHNG ANDREW B·Filed 2010·Granted Mar 19, 2013·33 cites·24 claims
- 0993US8490043B2Standard cells having transistors annotated for gate-length biasingGUPTA PUNEET·Filed 2010·Granted Jul 16, 2013·16 cites·16 claims
- 1093US8127266B1Gate-length biasing for digital circuit optimizationGUPTA PUNEET·Filed 2008·Granted Feb 28, 2012·22 cites·20 claims
- 1193US7814456B2Method and system for topography-aware reticle enhancementTELA INNOVATIONS INC·Filed 2005·Granted Oct 12, 2010·21 cites·18 claims
- 1292US7716612B1Method and system for integrated circuit optimization by using an optimized standard-cell libraryTELA INNOVATIONS INC·Filed 2006·Granted May 11, 2010·43 cites·30 claims
- 1389US8024675B1Method and system for wafer topography-aware integrated circuit design analysis and optimizationTELA INNOVATIONS INC·Filed 2006·Granted Sep 20, 2011·26 cites·45 claims
- 1488US7730432B1Method and system for reshaping a transistor gate in an integrated circuit to achieve a target objectiveTELA INNOVATIONS INC·Filed 2006·Granted Jun 1, 2010·32 cites·5 claims
- 1587US9922161B2IC layout adjustment method and tool for improving dielectric reliability at interconnectsUNIV CALIFORNIA·Filed 2014·Granted Mar 20, 2018·15 cites·31 claims
- 1686US8635583B2Standard cells having transistors annotated for gate-length biasingGUPTA PUNEET·Filed 2012·Granted Jan 21, 2014·6 cites·16 claims
- 1785US8103981B2Tool for modifying mask design layoutKAHNG ANDREW B·Filed 2009·Granted Jan 24, 2012·11 cites·17 claims
- 1881US7062743B2Floorplan evaluation, global routing, and buffer insertion for integrated circuitsUNIV CALIFORNIA·Filed 2003·Granted Jun 13, 2006·41 cites·24 claims
- 1980US8756555B2Standard cells having transistors annotated for gate-length biasingGUPTA PUNEET·Filed 2012·Granted Jun 17, 2014·3 cites·35 claims
- 2077US10713406B2Multi-die IC layout methods with awareness of mix and match die integrationUNIV CALIFORNIA·Filed 2016·Granted Jul 14, 2020·3 cites·16 claims
- 2174US7945870B2Method and apparatus for detecting lithographic hotspots in a circuit layoutUNIV CALIFORNIA·Filed 2007·Granted May 17, 2011·7 cites·15 claims
- 2273US7627849B1System and method for varying the starting conditions for a resolution enhancement program to improve the probability that design goals will be metTELA INNOVATIONS INC·Filed 2006·Granted Dec 1, 2009·3 cites·13 claims
- 2372US7614032B2Method for correcting a mask design layoutUNIVERISITY OF CALIFORNIA·Filed 2006·Granted Nov 3, 2009·4 cites·13 claims
- 2470US9069926B2Standard cells having transistors annotated for gate-length biasingTELA INNOVATIONS INC·Filed 2014·Granted Jun 30, 2015·1 cites·30 claims
- 2569US8949768B2Standard cells having transistors annotated for gate-length biasingGUPTA PUNEET·Filed 2012·Granted Feb 3, 2015·1 cites·49 claims
- 2668US7745239B1Arrangement of fill unit elements in an integrated circuit interconnect layerTELA INNOVATIONS INC·Filed 2006·Granted Jun 29, 2010·5 cites·6 claims
- 2767US7676772B1Layout description having enhanced fill annotationTELA INNOVATIONS INC·Filed 2006·Granted Mar 9, 2010·6 cites·13 claims
- 2865US7823098B1Method of designing a digital circuit by correlating different static timing analyzersTELA INNOVATIONS INC·Filed 2006·Granted Oct 26, 2010·4 cites·7 claims
- 2964US7865856B1System and method for performing transistor-level static performance analysis using cell-level static analysis toolsTELA INNOVATIONS INC·Filed 2008·Granted Jan 4, 2011·3 cites·11 claims
- 3059US9202003B2Gate-length biasing for digital circuit optimizationTELA INNOVATIONS INC·Filed 2014·Granted Dec 1, 2015·0 cites·27 claims
- 3157US9166567B2Data-retained power-gating circuit and devices including the samePARK BONG IL·Filed 2014·Granted Oct 20, 2015·2 cites·16 claims
- 3256US8869094B2Standard cells having transistors annotated for gate-length biasingGUPTA PUNEET·Filed 2012·Granted Oct 21, 2014·0 cites·48 claims
- 3347US9229686B2Accuracy configurable adders and methodsKAHNG ANDREW B·Filed 2012·Granted Jan 5, 2016·0 cites·21 claims
- 3447US8073977B2Internet telephony through hostsCOX JONATHAN·Filed 2004·Granted Dec 6, 2011·2 cites·19 claims
- 3538US6047117ADiffusion-based method and apparatus for determining circuit interconnect voltage responseUNIV CALIFORNIA·Filed 1997·Granted Apr 4, 2000·6 cites·10 claims
- 3637US2007033558A1Method and system for reshaping metal wires in VLSI designBLAZE DFM INC·Filed 2005·Application pending·0 cites
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