Inventor · disambiguated record
Stuart M. Burns
Also filed as: BURNS JR STUART MCALLISTER · BURNS STUART M
17 granted patents·1,454 citations·filing 1996–1999
96Inventor score
Top patents by PatentIndex Score
17 records- 0198US6077745ASelf-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell arrayIBM·Filed 1997·Granted Jun 20, 2000·277 cites·14 claims
- 0297US5874760A4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolationIBM·Filed 1997·Granted Feb 23, 1999·240 cites·10 claims
- 0396US6040210A2F-square memory cell for gigabit memory applicationsIBM·Filed 1998·Granted Mar 21, 2000·101 cites·11 claims
- 0494US5990509A2F-square memory cell for gigabit memory applicationsIBM·Filed 1997·Granted Nov 23, 1999·160 cites·12 claims
- 0593US6034389ASelf-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell arrayIBM·Filed 1997·Granted Mar 7, 2000·154 cites·11 claims
- 0691US6033957A4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolationIBM·Filed 1997·Granted Mar 7, 2000·81 cites·10 claims
- 0789US6013548ASelf-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell arrayIBM·Filed 1997·Granted Jan 11, 2000·99 cites·12 claims
- 0877US6258679B1Sacrificial silicon sidewall for damascene gate formationIBM·Filed 1999·Granted Jul 10, 2001·41 cites·24 claims
- 0976US6143635AField effect transistors with improved implants and method for making such transistorsIBM·Filed 1999·Granted Nov 7, 2000·37 cites·29 claims
- 1075US6040214AMethod for making field effect transistors having sub-lithographic gates with vertical side wallsIBM·Filed 1998·Granted Mar 21, 2000·47 cites·29 claims
- 1175US5895273ASilicon sidewall etchingIBM·Filed 1997·Granted Apr 20, 1999·48 cites·20 claims
- 1274US5976986ALow pressure and low power C12 /HC1 process for sub-micron metal etchingIBM·Filed 1996·Granted Nov 2, 1999·50 cites·13 claims
- 1367US6461529B1Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch schemeIBM·Filed 1999·Granted Oct 8, 2002·34 cites·4 claims
- 1467US5846884AMethods for metal etching with reduced sidewall build up during integrated circuit manufacturingSIEMENS AG·Filed 1997·Granted Dec 8, 1998·34 cites·21 claims
- 1565US6268226B1Reactive ion etch loading measurement techniqueIBM·Filed 1999·Granted Jul 31, 2001·31 cites·19 claims
- 1650US5759920AProcess for making doped polysilicon layers on sidewallsIBM·Filed 1996·Granted Jun 2, 1998·15 cites·21 claims
- 1738US6593617B1Field effect transistors with vertical gate side walls and method for making such transistorsIBM·Filed 1998·Granted Jul 15, 2003·5 cites·13 claims
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